公开(公告)号：US10958079B2

公开(公告)日：2021-03-23

申请号：US15939120

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Xiaosen Liu ,  Khondker Z. Ahmed ,  Vivek K. De ,  Nachiket V. Desai ,  Suhwan Kim ,  Harish K. Krishnamurthy ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav A. Vaidya ,  Sriram R. Vangal

IPC: H02J1/00 ,  H02J3/00 ,  H02J3/38 ,  H02M3/156 ,  G05F1/67 ,  H02M1/10 ,  H02M3/07 ,  H02M1/00

Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

公开(公告)号：US10217509B2

公开(公告)日：2019-02-26

申请号：US15495954

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C11/419 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C5/14

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US09787571B2

公开(公告)日：2017-10-10

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/26 ,  H04L12/727 ,  H04L12/933 ,  H04L12/773 ,  G06F15/78

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

公开(公告)号：US09633716B2

公开(公告)日：2017-04-25

申请号：US14989762

申请日：2016-01-06

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C8/08 ,  G11C11/417 ,  G11C7/12 ,  G11C8/10 ,  G11C11/418 ,  G11C13/00 ,  G11C5/14 ,  G11C29/02 ,  G11C11/412 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US09594625B2

公开(公告)日：2017-03-14

申请号：US14878985

申请日：2015-10-08

Applicant: INTEL CORPORATION

Inventor： Keith A. Bowman ,  James W. Tschanz ,  Nam Sung Kim ,  Janice C. Lee ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Tanay Karnik ,  Vivek K. De

IPC: G06F11/07 ,  G06F1/10 ,  H03K3/037 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G06F1/10 ,  G06F11/0706 ,  G06F11/0757 ,  G06F11/0793 ,  H03K3/0375

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract translation: 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

公开(公告)号：US20160173090A1

公开(公告)日：2016-06-16

申请号：US14572031

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Sandip Kundu ,  James W. Tschanz ,  Vivek K. De

IPC: H03K19/003 ,  H03K3/037

CPC classification number: H03K19/00323 ,  H03K5/26

Abstract: Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

Abstract translation: 描述了用于检测或修复最小延迟误差的装置和方法。 该装置可以包括用于接收时钟信号和数据路径信号的最小延迟误差检测器（MDED），并且基于所接收的数据路径信号和时钟信号来检测数据路径中的最小延迟误差（MDE）。 可以通过调整耦合到MDED的一个或多个区域时钟缓冲器来修复MDE。 此外，该装置可以包括用于在正常系统操作期间检测和修复MDE的最小延迟路径副本（MDPR）。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160141022A1

公开(公告)日：2016-05-19

申请号：US14830679

申请日：2015-08-19

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah ,  James W. Tschanz ,  Bibiche M. Geuskens ,  Vivek K. De

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/413

Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Abstract translation: 描述了一种用于存储元件的写入最小电源电压的自感应降低的装置。 该装置包括：具有耦合到第一电源节点的交叉耦合的反相器的存储元件; 耦合到所述第一供应节点和第二供应节点的功率设备，所述第二供应节点耦合到电源; 以及具有耦合到字线的栅极端子，耦合到存储器元件的第一端子和耦合到位线的第二端子的存取装置，该位线可操作以在写入之前预放电到逻辑低电平 操作。