公开(公告)号：US20160093625A1

公开(公告)日：2016-03-31

申请号：US14502728

申请日：2014-09-30

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Imran Hashim ,  Prashant B. Phatak

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/55

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. The dielectric layer may include zirconium oxide or doped zirconium oxide. In some embodiments, the conductive metal oxide layer includes niobium oxide.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 电介质层可以包括氧化锆或掺杂氧化锆。 在一些实施例中，导电金属氧化物层包括氧化铌。

公开(公告)号：US09099430B2

公开(公告)日：2015-08-04

申请号：US14135491

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Xiangxin Rui

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10805

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract translation: 在形成用于微电子逻辑电路中的去耦电容器中使用基于氧化锆的电介质材料。 在一些实施方案中，掺杂氧化锆基电介质。 在一些实施方案中，掺杂剂包括铝，硅或钇中的至少一种。 在一些实施方案中，基于氧化锆的电介质形成为氧化锆和掺杂剂金属氧化物的纳米氨酸盐。

公开(公告)号：US20150179730A1

公开(公告)日：2015-06-25

申请号：US14135491

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Xiangxin Rui

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10805

Abstract: A zirconium oxide based dielectric material is used in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the zirconium oxide based dielectric is doped. In some embodiments, the dopant includes at least one of aluminum, silicon, or yttrium. In some embodiments, the zirconium oxide based dielectric is formed as a nanolaminate of zirconium oxide and a dopant metal oxide.

Abstract translation: 在形成用于微电子逻辑电路中的去耦电容器中使用基于氧化锆的电介质材料。 在一些实施方案中，掺杂氧化锆基电介质。 在一些实施方案中，掺杂剂包括铝，硅或钇中的至少一种。 在一些实施方案中，基于氧化锆的电介质形成为氧化锆和掺杂剂金属氧化物的纳米氨酸盐。

公开(公告)号：US08980744B2

公开(公告)日：2015-03-17

申请号：US13675852

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L27/108 ,  H01L49/02 ,  C23C16/40

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US20140183696A1

公开(公告)日：2014-07-03

申请号：US13737138

申请日：2013-01-09

Applicant: INTERMOLECULAR INC.

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

公开(公告)号：US08546236B2

公开(公告)日：2013-10-01

申请号：US13738866

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/20 ,  H01L21/31

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

公开(公告)号：US08541828B2

公开(公告)日：2013-09-24

申请号：US13668488

申请日：2012-11-05

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/3141 ,  C23C16/02 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31604 ,  H01L28/91

Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.

Abstract translation: 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种将氧化钛层沉积在暴露的金属上，其中氧化钛层包括至少一部分金红石型氧化钛。