公开(公告)号：US20150146341A1

公开(公告)日：2015-05-28

申请号：US14092431

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  David Paul Brunco ,  Karthik Ramani ,  Dina Triyoso

IPC: H01G4/10 ,  C23C16/455 ,  H01G4/30

CPC classification number: H01G4/10 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45525 ,  H01G4/085 ,  H01G4/1281 ,  H01G4/306 ,  H01G4/33 ,  H01L28/40

Abstract: A thin sub-layer ( 12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.

Abstract translation: 在高k（k> 12）主体材料的较厚层（〜30-100）的下面，上方或内部形成杂质的薄亚层（<15Å）。 子层可以通过原子层沉积（ALD）形成。 层和子层进行退火以形成复合介电层。 主体材料结晶，但晶格和晶界在杂质子层附近被破坏，阻碍了电子迁移。 杂质可以是具有比高k材料低的介电常数的材料，以如此小的相对量添加复合电介质仍然高k。 可以通过在两个电极之间形成复合介电层来制造金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20140183696A1

公开(公告)日：2014-07-03

申请号：US13737138

申请日：2013-01-09

Applicant: INTERMOLECULAR INC.

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

公开(公告)号：US08815695B2

公开(公告)日：2014-08-26

申请号：US13727898

申请日：2012-12-27

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/92 ,  H01L21/8242 ,  H01L21/316 ,  H01L27/04 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

公开(公告)号：US09297775B2

公开(公告)日：2016-03-29

申请号：US14285921

申请日：2014-05-23

Applicant: Intermolecular Inc.

Inventor： Edwin Adhiprakasha ,  Sean Barstow ,  Ashish Bodke ,  Zhendong Hong ,  Usha Raghuram ,  Karthik Ramani ,  Vivian Ryan ,  Jingang Su ,  Xunyuan Zhang

IPC: H01L27/20 ,  G01N27/20 ,  C23C14/34 ,  C23C14/54 ,  C23C14/06 ,  G01N27/04

CPC classification number: G01N27/20 ,  C23C14/06 ,  C23C14/14 ,  C23C14/3464 ,  C23C14/54 ,  C23C14/548 ,  G01N27/041

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

公开(公告)号：US20150338362A1

公开(公告)日：2015-11-26

申请号：US14285921

申请日：2014-05-23

Applicant: Intermolecular Inc.

Inventor： Edwin Adhiprakasha ,  Sean Barstow ,  Ashish Bodke ,  Zhendong Hong ,  Usha Raghuram ,  Karthik Ramani ,  Vivian Ryan ,  Jingang Su ,  Xunyuan Zhang

IPC: G01N27/20 ,  G01N27/04 ,  C23C14/06 ,  C23C14/34 ,  C23C14/54

CPC classification number: G01N27/20 ,  C23C14/06 ,  C23C14/14 ,  C23C14/3464 ,  C23C14/54 ,  C23C14/548 ,  G01N27/041

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract translation: 使用通过不同大小的孔溅射或共溅射的测试结构组合地筛选用于小规模互连（例如铜）的阻挡层，阻挡层和种子层。 在退火之前和/或之后测量与导电性，扩散阻挡和粘附有关的各种特性（例如，电阻率，结晶形态，表面粗糙度）并进行比较以获得材料和工艺参数，以通过互连实现高导电性的低扩散。 示例结果表明，一些钽 - 钛屏障的配方可以替代较厚的钽/氮化钽叠层，在某些情况下可以在Ta-Ti和铜之间具有Cu-Mn种子层。

公开(公告)号：US20150021772A1

公开(公告)日：2015-01-22

申请号：US13943418

申请日：2013-07-16

Applicant: Intermolecular Inc.

Inventor： Edwin Adhiprakasha ,  Sandip Niyogi ,  Karthik Ramani ,  Vivian Ryan

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/2855 ,  C23C14/165 ,  C23C14/3492 ,  C23C14/352 ,  C23C14/5806 ,  H01J37/3408 ,  H01J37/3429 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A barrier film including at least one ferromagnetic metal (e.g., nickel) and at least one refractory metal (e.g., tantalum) effectively blocks copper diffusion and facilitates uniform contiguous (non-agglomerating) deposition of copper layers less than 100 Å thick. Methods of forming the metal barrier include co-sputtering the component metals from separate targets. Using high-productivity combinatorial (HPC) apparatus and methods, the proportions of the component metals can be optimized. Gradient compositions can be deposited by varying the plasma power or throw distance of the separate targets.

Abstract translation: 包括至少一种铁磁金属（例如镍）和至少一种难熔金属（例如钽）的阻挡膜有效地阻止铜扩散并促进小于100埃的铜层的均匀连续（非聚集）沉积。 形成金属屏障的方法包括从分离的靶共溅射组分金属。 使用高生产率组合（HPC）设备和方法，可以优化组分金属的比例。 可以通过改变分离靶的等离子体功率或投射距离来沉积梯度组合物。

公开(公告)号：US08836002B2

公开(公告)日：2014-09-16

申请号：US13738794

申请日：2013-01-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

公开(公告)号：US08542523B2

公开(公告)日：2013-09-24

申请号：US13738855

申请日：2013-01-10

Applicant: Intermolecular Inc.

Inventor： Karthik Ramani ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: G11C11/00

CPC classification number: H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.

公开(公告)号：US20130119515A1

公开(公告)日：2013-05-16

申请号：US13738855

申请日：2013-01-10

Applicant: Intermolecular Inc.

Inventor： Karthik Ramani ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括形成第一电极膜。 第一电极膜包括导电二元金属化合物和掺杂剂。 掺杂剂可以在第一电极膜内具有均匀或不均匀的浓度。 在第一电极膜上形成高k电介质膜。 在绝缘膜上形成第二电极膜。 第二电极膜包括导电二元金属化合物和掺杂剂。 掺杂剂可以在第二电极膜内具有均匀或不均匀的浓度。 选择掺杂剂及其分布，使得如果将电极用作后续层形成的模板结构，则电极表面的晶体结构不会降解。 此外，选择掺杂剂及其分布使得电极的功函数不降解。

公开(公告)号：US20140187015A1

公开(公告)日：2014-07-03

申请号：US13727898

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.