公开(公告)号：US20200152550A1

公开(公告)日：2020-05-14

申请号：US16189787

申请日：2018-11-13

Applicant: International Business Machines Corporation

Inventor： Benjamin Wunsch ,  Joshua T. Smith ,  Stacey Gifford

IPC: H01L23/48 ,  H01L23/29 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/306 ,  H01L21/56 ,  H01L21/48 ,  H01L21/02

Abstract: Devices and methods that can facilitate electrically conductive deterministic lateral displacement (DLD) pillar array components are provided. According to an embodiment, a device can comprise a substrate that can have a channel that can comprise electrically conductive pillar components that can be coupled to one or more electrodes. The device can further comprise a seal layer that can be coupled to the substrate that seals the one or more electrodes.

公开(公告)号：US20190151774A1

公开(公告)日：2019-05-23

申请号：US15815846

申请日：2017-11-17

Applicant: International Business Machines Corporation

Inventor： Stacey Gifford ,  Sung-Cheol Kim ,  Joshua Smith ,  Benjamin Wunsch

IPC: B01D17/02 ,  B01D21/24

Abstract: A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.

公开(公告)号：US12042770B2

公开(公告)日：2024-07-23

申请号：US17520713

申请日：2021-11-07

Applicant: International Business Machines Corporation

Inventor： Joshua T. Smith ,  Stacey Gifford ,  Sung-Cheol Kim ,  Benjamin Wunsch

IPC: B01D71/02 ,  B01D29/00 ,  B01D29/44 ,  B01L3/00 ,  B81C1/00

CPC classification number: B01D71/0213 ,  B01D29/0093 ,  B01D29/44 ,  B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L3/565 ,  B81C1/00119 ,  B01L2300/0861 ,  B01L2300/0896 ,  B01L2300/12 ,  B01L2400/0487 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133

Abstract: An exemplary method includes forming a sacrificial layer along sidewalls of an array of trenches that are indented into a substrate, depositing a fill layer over the sacrificial layer, and then creating an array of gaps between the fill layer and the substrate by removing the sacrificial layer along the sidewalls of the trenches, while maintaining a structural connection between the substrate and the fill layer at the floors of the trenches. The method further includes covering the substrate, the fill layer, and the gaps with a cap layer that seal fluid-tight against the substrate and the fill layer. The method further includes indenting a first reservoir and a second reservoir through the cap layer, and into the substrate and the fill layer, across the lengths of the array of gaps, so that the array of gaps connects the first reservoir in fluid communication with the second reservoir.

公开(公告)号：US11651925B2

公开(公告)日：2023-05-16

申请号：US17146515

申请日：2021-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua T. Smith ,  Benjamin Wunsch

IPC: H01L21/00 ,  H01J21/10 ,  H01J1/304 ,  H01L21/3215 ,  H01L29/417

CPC classification number: H01J21/105 ,  H01J1/3042 ,  H01L21/3215 ,  H01L29/41725 ,  H01J2201/319

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

公开(公告)号：US11612889B2

公开(公告)日：2023-03-28

申请号：US17162002

申请日：2021-01-29

Applicant: International Business Machines Corporation

Inventor： Evan Colgan ,  Joshua T. Smith ,  Benjamin Wunsch

IPC: B81B7/00 ,  B01L3/00 ,  B81C1/00 ,  G01N15/02

Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.

公开(公告)号：US11440002B2

公开(公告)日：2022-09-13

申请号：US16168292

申请日：2018-10-23

Applicant: International Business Machines Corporation

Inventor： Joshua T. Smith ,  Robert Bruce ,  Jyotica V. Patel ,  Benjamin Wunsch

IPC: B81B7/04 ,  B01L3/00

Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

公开(公告)号：US20220055893A1

公开(公告)日：2022-02-24

申请号：US17520713

申请日：2021-11-07

Applicant: International Business Machines Corporation

Inventor： Joshua T. Smith ,  Stacey Gifford ,  Sung-Cheol Kim ,  Benjamin Wunsch

IPC: B81C1/00 ,  B01D29/44 ,  B01D29/00 ,  B01L3/00

Abstract: An exemplary method includes forming a sacrificial layer along sidewalls of an array of trenches that are indented into a substrate, depositing a fill layer over the sacrificial layer, and then creating an array of gaps between the fill layer and the substrate by removing the sacrificial layer along the sidewalls of the trenches, while maintaining a structural connection between the substrate and the fill layer at the floors of the trenches. The method further includes covering the substrate, the fill layer, and the gaps with a cap layer that seal fluid-tight against the substrate and the fill layer. The method further includes indenting a first reservoir and a second reservoir through the cap layer, and into the substrate and the fill layer, across the lengths of the array of gaps, so that the array of gaps connects the first reservoir in fluid communication with the second reservoir.

公开(公告)号：US20210166908A1

公开(公告)日：2021-06-03

申请号：US17146515

申请日：2021-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua T. Smith ,  Benjamin Wunsch

IPC: H01J21/10 ,  H01J1/304 ,  H01L21/3215 ,  H01L29/417

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

公开(公告)号：US10937620B2

公开(公告)日：2021-03-02

申请号：US16142208

申请日：2018-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua T. Smith ,  Benjamin Wunsch

IPC: H01L21/00 ,  H01J21/10 ,  H01J1/304 ,  H01L21/3215 ,  H01L29/417

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

公开(公告)号：US20200098534A1

公开(公告)日：2020-03-26

申请号：US16142208

申请日：2018-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Joshua T. Smith ,  Benjamin Wunsch

IPC: H01J21/10 ,  H01J1/304 ,  H01L29/417 ,  H01L21/3215

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.