公开(公告)号：US20200185381A1

公开(公告)日：2020-06-11

申请号：US16788229

申请日：2020-02-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/098

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US20200066881A1

公开(公告)日：2020-02-27

申请号：US16664060

申请日：2019-10-25

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/423

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.

公开(公告)号：US20200066604A1

公开(公告)日：2020-02-27

申请号：US16106412

申请日：2018-08-21

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a substrate, and forming one or more vertical transport field-effect transistors from the plurality of fins, the plurality of fins providing channels for the one or more vertical transport field-effect transistors. The method also includes forming a gate stack for the one or more vertical transport field-effect transistors surrounding at least a portion of the plurality of fins, the gate stack including a gate dielectric formed over the plurality of fins, a work function metal layer formed over the gate dielectric, and a gate conductor formed over the work function metal layer. The gate stack comprises a box profile in an area between at least two adjacent ones of the plurality of fins.

公开(公告)号：US10535754B2

公开(公告)日：2020-01-14

申请号：US16000563

申请日：2018-06-05

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.

公开(公告)号：US20200013877A1

公开(公告)日：2020-01-09

申请号：US16553912

申请日：2019-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

公开(公告)号：US20200006553A1

公开(公告)日：2020-01-02

申请号：US16023535

申请日：2018-06-29

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

公开(公告)号：US20190326435A1

公开(公告)日：2019-10-24

申请号：US15955822

申请日：2018-04-18

Applicant: International Business Machines Corporation

Inventor： Chun Wing Yeung ,  ChoongHyun Lee ,  Jingyun Zhang ,  Robin Hsin Kuo Chao ,  Heng Wu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a substrate, wherein sidewalls of the at least one fin includes a first portion proximate a top surface of the substrate having a tapered profile and a second portion disposed above the first portion. The method also includes forming a bottom source/drain region surrounding at least part of the first portion of the sidewalls of the at least one fin having the tapered profile and forming a bottom spacer disposed over a top surface of the bottom source/drain region surrounding at least part of the second portion of the sidewalls of the at least one fin. The at least one fin provides a channel for a vertical field-effect transistor.

公开(公告)号：US10395080B2

公开(公告)日：2019-08-27

申请号：US15958021

申请日：2018-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hemanth Jagannathan ,  ChoongHyun Lee ,  Richard G. Southwick, III

IPC: G06K7/10 ,  G06K7/14 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238

Abstract: A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.

公开(公告)号：US10297671B2

公开(公告)日：2019-05-21

申请号：US16040978

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee ,  Vijay Narayanan ,  Koji Watanabe

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66

Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.

公开(公告)号：US10283620B2

公开(公告)日：2019-05-07

申请号：US15416281

申请日：2017-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.