公开(公告)号：US20230155009A1

公开(公告)日：2023-05-18

申请号：US17528279

申请日：2021-11-17

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Ruilong Xie ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225

CPC classification number: H01L29/66977 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78684 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/2252 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A semiconductor tunnel FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

公开(公告)号：US11257934B2

公开(公告)日：2022-02-22

申请号：US16752817

申请日：2020-01-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/225 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

公开(公告)号：US10943835B2

公开(公告)日：2021-03-09

申请号：US16153020

申请日：2018-10-05

Applicant: International Business Machines Corporation

Inventor： ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L21/74 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/10 ,  H01L23/535 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.

公开(公告)号：US10943816B2

公开(公告)日：2021-03-09

申请号：US16374279

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  ChoongHyun Lee

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, and patterning the hardmask layer into a plurality of hardmask portions. The method also includes forming a liner layer on the plurality of hardmask portions, and removing a portion of the liner layer from at least one hardmask portion of the plurality of hardmask portions. The removing exposes one or more surfaces of the at least one hardmask portion. In the method, the at least one hardmask portion and a remaining portion of the liner layer are removed. A pattern of remaining ones of the plurality of hardmask portions are transferred to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.

公开(公告)号：US20200321245A1

公开(公告)日：2020-10-08

申请号：US16374279

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  ChoongHyun Lee

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, and patterning the hardmask layer into a plurality of hardmask portions. The method also includes forming a liner layer on the plurality of hardmask portions, and removing a portion of the liner layer from at least one hardmask portion of the plurality of hardmask portions. The removing exposes one or more surfaces of the at least one hardmask portion. In the method, the at least one hardmask portion and a remaining portion of the liner layer are removed. A pattern of remaining ones of the plurality of hardmask portions are transferred to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.

公开(公告)号：US10770546B2

公开(公告)日：2020-09-08

申请号：US16142565

申请日：2018-09-26

Applicant: International Business Machines Corporation

Inventor： ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/00 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of pillars on a substrate. Each pillar of the plurality of pillars includes a silicon germanium portion. In the method, a layer of germanium oxide is deposited on the plurality of pillars, and a thermal annealing process is performed to convert outer regions of the silicon germanium portions into a plurality of silicon nanotubes. Each silicon nanotube of the plurality of silicon nanotubes surrounds a silicon germanium core portion. The method also includes exposing top surfaces of each of the silicon germanium core portions, and selectively removing each of the silicon germanium core portions with respect to the plurality of silicon nanotubes to create a plurality of gaps.

公开(公告)号：US20200259000A1

公开(公告)日：2020-08-13

申请号：US16273331

申请日：2019-02-12

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

公开(公告)号：US10665714B2

公开(公告)日：2020-05-26

申请号：US16023535

申请日：2018-06-29

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

公开(公告)号：US10607990B2

公开(公告)日：2020-03-31

申请号：US15590627

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L27/098 ,  H01L21/8234 ,  H01L21/28

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US20200066903A1

公开(公告)日：2020-02-27

申请号：US16106379

申请日：2018-08-21

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Brent A. Anderson ,  ChoongHyun Lee ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.