公开(公告)号：US20220392995A1

公开(公告)日：2022-12-08

申请号：US17341489

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L49/02 ,  H01L29/51

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

公开(公告)号：US11106850B2

公开(公告)日：2021-08-31

申请号：US16559976

申请日：2019-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Wolpert ,  Timothy A. Schell ,  Erwin Behnen ,  Leon Sigal

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/398

Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

公开(公告)号：US10699050B2

公开(公告)日：2020-06-30

申请号：US15969841

申请日：2018-05-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Wolpert ,  Erwin Behnen ,  Lawrence A. Clevenger ,  Patrick Watson ,  Chih-Chao Yang ,  Timothy A. Schell

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394 ,  G06F30/398

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

公开(公告)号：US20250054863A1

公开(公告)日：2025-02-13

申请号：US18448933

申请日：2023-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Takashi Ando ,  David Wolpert

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

公开(公告)号：US12176289B2

公开(公告)日：2024-12-24

申请号：US17656368

申请日：2022-03-24

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Terence Hook

IPC: H01L23/528 ,  H01L27/092

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

公开(公告)号：US20240371729A1

公开(公告)日：2024-11-07

申请号：US18312613

申请日：2023-05-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Biswanath Senapati ,  David Wolpert ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Leon Sigal ,  Brent A. Anderson ,  Albert M. Chu ,  Reinaldo Vega

IPC: H01L23/48 ,  H01L29/417

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

公开(公告)号：US20240194236A1

公开(公告)日：2024-06-13

申请号：US18065195

申请日：2022-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Nicholas Anthony Lanzillo

IPC: G11C11/22 ,  H10B53/30

CPC classification number: G11C11/221 ,  G11C11/2273 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

公开(公告)号：US20240136281A1

公开(公告)日：2024-04-25

申请号：US17969773

申请日：2022-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  Takashi Ando ,  David Wolpert ,  Albert M. Chu ,  Albert M. Young

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/32139 ,  H01L21/76892 ,  H01L23/5226

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

公开(公告)号：US11941340B2

公开(公告)日：2024-03-26

申请号：US17402710

申请日：2021-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Alexander Bowen ,  Gerald L Strevig, III ,  Amanda Christine Venton ,  Robert Mahlon Averill, III ,  Adam P. Matheny ,  David Wolpert ,  Mitchell R. DeHond

IPC: G06F30/39 ,  G06F30/398

CPC classification number: G06F30/398

Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

公开(公告)号：US20240096793A1

公开(公告)日：2024-03-21

申请号：US17933078

申请日：2022-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  Takashi Ando ,  David Wolpert

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/306 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/0226 ,  H01L21/30604 ,  H01L23/481 ,  H01L23/5226

Abstract: A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.