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公开(公告)号:US20200303339A1
公开(公告)日:2020-09-24
申请号:US16358658
申请日:2019-03-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: CHARLES L. ARVIN , Clement J. Fortin , Christopher D. Muzzy , Krishna R. Tunga , Thomas Weiss
IPC: H01L23/00 , H01L23/532
Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.
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公开(公告)号:US10665524B2
公开(公告)日:2020-05-26
申请号:US15671734
申请日:2017-08-08
Applicant: International Business Machines Corporation
Inventor: Kamal K. Sikka , Krishna R. Tunga
IPC: H01L23/367 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/373 , H01L23/42
Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
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33.
公开(公告)号:US20200160228A1
公开(公告)日:2020-05-21
申请号:US16191894
申请日:2018-11-15
Applicant: International Business Machines Corporation
Inventor: Mahmoud Amin , Zhenxing Bi , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Krishna R. Tunga
IPC: G06N99/00
Abstract: Embodiments of the invention provide a computer-implemented method of generating individualized strategies for a group of team members pursing a team objective based on an optimized team strategy. A team objective and a plurality of inputs associated with a plurality of team members is received at a strategy engine. A training model is applied to the plurality of inputs from the first plurality of team members to generate a plurality of individualized strategies for the first plurality of team members to achieve the team objective. An optimized team strategy based on the plurality of individualized strategies is generated and the individualized strategies are communicated to each team member wherein each team member pursuing their individualized strategy leads to achieving the team objective.
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公开(公告)号:US20190295921A1
公开(公告)日:2019-09-26
申请号:US15934972
申请日:2018-03-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Charles L. Arvin , Marcus E. Interrante , Thomas E. Lombardi , Hilton T. Toy , Krishna R. Tunga , Thomas Weiss
IPC: H01L23/373 , H05K1/02 , H01L23/42 , H01L23/538 , H01L23/00
Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.
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公开(公告)号:US10420502B2
公开(公告)日:2019-09-24
申请号:US15801720
申请日:2017-11-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Mahmoud Amin , Zhenxing Bi , Lawrence A. Clevenger , Leigh Anne H. Clevenger , Krishna R. Tunga
Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.
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36.
公开(公告)号:US10276535B2
公开(公告)日:2019-04-30
申请号:US15794192
申请日:2017-10-26
Applicant: International Business Machines Corporation
Inventor: Anson J. Call , Vijayeshwar D. Khanna , David J. Russell , Krishna R. Tunga
IPC: H01L21/44 , H01L23/00 , H01L23/498 , H01L21/48
Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
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公开(公告)号:US20180301355A1
公开(公告)日:2018-10-18
申请号:US15486749
申请日:2017-04-13
Applicant: International Business Machines Corporation
Inventor: Tuhin Sinha , Krishna R. Tunga
Abstract: A method to control warpage in a semiconductor chip package that includes: attaching a semiconductor chip to a semiconductor chip package; attaching a stiffener to the semiconductor chip package so that the semiconductor chip is contained within the stiffener, the stiffener having a coefficient of thermal expansion (CTE) less than that of the substrate on which the chip is assembled; attaching the semiconductor chip package to a laminate substrate; and removing the stiffener.
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公开(公告)号:US20180082919A1
公开(公告)日:2018-03-22
申请号:US15671734
申请日:2017-08-08
Applicant: International Business Machines Corporation
Inventor: Kamal K. Sikka , Krishna R. Tunga
IPC: H01L23/367 , H01L23/00 , H01L21/48 , H01L21/56
CPC classification number: H01L23/3675 , H01L21/563 , H01L23/373 , H01L23/3736 , H01L23/42 , H01L24/16 , H01L2224/16157
Abstract: An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device.
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公开(公告)号:US20180076101A1
公开(公告)日:2018-03-15
申请号:US15813536
申请日:2017-11-15
Applicant: International Business Machines Corporation
Inventor: Sushumna Iruvanti , Shidong Li , Marek A. Orlowski , David L. Questad , Tuhin Sinha , Krishna R. Tunga , Thomas A. Wassick , Randall J. Werner , Jeffrey A. Zitz
IPC: H01L21/66 , H01L21/48 , H01L23/498 , G06F17/50
CPC classification number: H01L22/32 , G06F17/5068 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L23/49866 , H01L2224/16225 , H01L2924/15311
Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.
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40.
公开(公告)号:US08860206B2
公开(公告)日:2014-10-14
申请号:US14041875
申请日:2013-09-30
Applicant: International Business Machines Corporation
Inventor: Kamal K. Sikka , Hilton T. Toy , Krishna R. Tunga , Jeffrey A. Zitz
CPC classification number: H01L23/04 , H01L21/50 , H01L23/10 , H01L23/562 , H01L24/32 , H01L24/83 , H01L2224/32245 , H01L2224/83191 , H01L2924/01322 , H01L2924/16251 , H01L2924/164 , H01L2924/166 , H01L2924/00
Abstract: A multi-chip electronic package and methods of manufacture are provided. The method includes adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting includes placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further includes lowering the lid until the pistons contact the chip shim. The method further includes separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further includes dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further includes sealing the lid to the chip carrier with sealant.
Abstract translation: 提供了一种多芯片电子封装及其制造方法。 该方法包括相对于芯片载体上的一个或多个芯片来调节一个或多个活塞的活塞位置。 调整包括将芯片垫片放置在芯片上,并将密封垫片放置在盖子和芯片载体之间。 密封垫片比芯片垫片厚。 该调节还包括降低盖直到活塞接触芯片垫片。 该方法还包括分离盖和芯片载体并移除芯片垫片和密封垫片。 该方法还包括将热界面材料分配在芯片上并降低盖子,直到填充有热界面材料的间隙大约为热界面材料的粒度。 该方法还包括用密封剂将盖子密封到芯片载体上。
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