公开(公告)号：US20160103736A1

公开(公告)日：2016-04-14

申请号：US14510350

申请日：2014-10-09

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Chen-Yong Cher ,  Meeta S. Gupta

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/20

Abstract: Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Abstract translation: 公开了处理器寄存器保护管理。 在实施例中，处理器寄存器保护管理的方法可以包括确定由编译器产生的可执行代码的敏感逻辑寄存器，产生识别敏感逻辑寄存器的纠错表，以及将错误校正表存储在由 处理器。 处理器可以被配置为生成由纠错表识别的敏感逻辑寄存器的重复寄存器。

公开(公告)号：US09298253B2

公开(公告)日：2016-03-29

申请号：US14026472

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3287 ,  G06F1/26 ,  Y02D10/171 ,  Y02D50/20

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.

Abstract translation: 为具有电源门控的集成电路提供了一种机制。 电源接头开关被配置为将多个电路中的任何一个连接到一个公共电压源，其中断电电路与公共电压源断开。 上电序列器包括初始阶段上电组件和最后阶段上电组件。 最后阶段上电组件被配置为执行关闭电路的上电过程的最后阶段，并且初始阶段上电组件被配置为执行关断电路的上电过程的初始阶段 。 响应于预测的上电请求，初始级上电组件被激活。

公开(公告)号：US20150206569A1

公开(公告)日：2015-07-23

申请号：US14320219

申请日：2014-06-30

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Xiaochen Guo ,  Hillery C. Hunter ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

IPC: G11C11/16

CPC classification number: A61G5/1075 ,  A61G5/02 ,  A61H3/00 ,  A61H2003/004 ,  A61H2201/0161 ,  A61H2201/1633 ,  Y10T29/49826

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

公开(公告)号：US20150177796A1

公开(公告)日：2015-06-25

申请号：US14134428

申请日：2013-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Victor Zyuban

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3296 ,  Y02D10/172

Abstract: According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors.

Abstract translation: 根据一个实施例，提供了一种系统，其包括至少一个电力选通部件和两个或更多个功率开关晶体管，其被配置为在公共供电轨道，至少一个电力门控部件和地面之间提供一个或多个导电路径 。 两个或更多个功率开关晶体管每个包括源极端子，漏极端子和被配置为控制源极和漏极端子之间的电流的栅极端子。 该系统还包括耦合到栅极端子的旋转电压控制，并且被配置为在至少一个电力门控部件被接通的同时，将在导通状态和截止状态之间旋转的一系列控制信号施加到每个栅极端子 。 开关激活比电平是可编程的，以将多个功率开关晶体管相对于功率开关晶体管的总数设置为导通状态。

公开(公告)号：US20140281605A1

公开(公告)日：2014-09-18

申请号：US13837655

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

Abstract translation: 实施例包括一种用于管理计算机系统中的电力的方法，所述计算机系统包括主处理器和包括供电单元的主动存储器设备，所述主存储器设备通过存储器链路与主处理器通信，所述动力单元包括处理元件。 该方法包括主处理器在程序线程上执行程序，遇到要由有源存储器件执行的代码的第一部分，通过第一命令改变有源存储器件上的供电单元的功率状态，基于 主处理器遇到第一部分代码，第一个命令包括一个存储命令。 该方法还包括处理元件在第二时间执行代码的第一部分，基于执行第一部分的处理元件，将主处理器的功率状态从功率使用状态改变到省电状态。

公开(公告)号：US12169792B2

公开(公告)日：2024-12-17

申请号：US16015986

申请日：2018-06-22

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Pradip Bose ,  Alper Buyuktosunoglu

IPC: G06N7/01 ,  G05D1/00 ,  G06N20/00 ,  H04L9/40 ,  H04L67/12

Abstract: In a first device, a local classification and a local classification confidence score corresponding to an event input are computed. At the first device in response to a broadcast request, a remote classification and a remote classification confidence score corresponding to the event input are received, the remote classification and the remote classification confidence score being computed at a second device. At the first device, a consensus classification including the most frequent classification from a set of all received remote classifications and the local classification is formed, provided the number of classifications including the most frequent classification exceeds a threshold. In response to a consensus classification confidence score corresponding to the consensus classification exceeding a confidence threshold, a local classification model is updated. Based on the local classification and the consensus classification, the event input is assigned to a classification.

公开(公告)号：US11810340B2

公开(公告)日：2023-11-07

申请号：US15825660

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V. Swaminathan ,  Swagath Venkataramani

IPC: G06V10/82 ,  G06N3/08 ,  G06N20/00 ,  G06F18/214 ,  G06F18/20 ,  G06N3/045 ,  G06V10/774

CPC classification number: G06V10/82 ,  G06F18/214 ,  G06F18/2148 ,  G06F18/285 ,  G06N3/045 ,  G06N3/08 ,  G06N20/00 ,  G06V10/7747

Abstract: A system includes a determination component that determines output for successively larger neural networks of a set; and a consensus component that determines consensus between a first neural network and a second neural network of the set. A linear chain of increasingly complex neural networks trained on progressively larger inputs is utilized (e.g., increasingly complex neural networks is generally representative of increased accuracy). Outputs of progressively networks are computed until a consensus point is reached—where two or more successive large networks yield a same inference output. At such point of consensus the larger neural network of the set reaching consensus can be deemed appropriately sized (or of sufficient complexity) for a classification task at hand.

公开(公告)号：US11620207B2

公开(公告)日：2023-04-04

申请号：US16736959

申请日：2020-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Pradip Bose

IPC: G06F11/34 ,  G06N20/00 ,  G06N5/04 ,  H04L67/289 ,  G06F9/50

Abstract: Various embodiments are provided for load balancing of machine learning operations in a computing environment by a processor. One or more machine learning operations performing inference or training operations may by dynamically balanced between one or more edge computing devices in a wireless communication network and a cloud computing system for increasing performance of a selected metric.

公开(公告)号：US11599795B2

公开(公告)日：2023-03-07

申请号：US15806393

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V Swaminathan ,  Augusto Vega ,  Swagath Venkataramani

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/082

Abstract: An N modular redundancy method, system, and computer program product include a computer-implemented N modular redundancy method for neural networks, the method including selectively replicating the neural network by employing one of checker neural networks and selective N modular redundancy (N-MR) applied only to critical computations.

公开(公告)号：US20220343218A1

公开(公告)日：2022-10-27

申请号：US17239812

申请日：2021-04-26

Applicant: International Business Machines Corporation

Inventor： Hazar Yueksel ,  Brian E. D. Kingsbury ,  Kush Raj Varshney ,  Pradip Bose ,  Dinesh C. Verma ,  Shiqiang Wang ,  Augusto Vega ,  ASHISH VERMA ,  SUPRIYO CHAKRABORTY

IPC: G06N20/20 ,  G06F11/34

Abstract: Embodiments relate to an input-encoding technique in conjunction with federation. Participating entities are arranged in a collaborative relationship. Each participating entity trains a machine learning model with an encoder on a training data set. The performance of each of the models is measured and at least one of the models is selectively identified based on the measured performance. An encoder of the selectively identified machine learning model is shared with each of the participating entities. The shared encoder is configured to be applied by the participating entities to train the first and second machine learning models, which are configured to be merged and shared in the federated learning environment.