公开(公告)号：US20210327751A1

公开(公告)日：2021-10-21

申请号：US16851167

申请日：2020-04-17

Applicant: International Business Machines Corporation

Inventor： Christopher J. Penny ,  Brent Anderson ,  Lawrence A. Clevenger ,  Robert Robison ,  Kisik Choi ,  Nicholas Anthony Lanzillo

IPC: H01L21/768 ,  H01L23/522

Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

公开(公告)号：US20210265201A1

公开(公告)日：2021-08-26

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US20210249351A1

公开(公告)日：2021-08-12

申请号：US16786393

申请日：2020-02-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768

Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.

公开(公告)号：US20210217696A1

公开(公告)日：2021-07-15

申请号：US16739556

申请日：2020-01-10

Applicant: International Business Machines Corporation

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.

公开(公告)号：US20210210379A1

公开(公告)日：2021-07-08

申请号：US16736478

申请日：2020-01-07

Applicant: International Business Machines Corporation

Inventor： Daniel James Dechene ,  Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.

公开(公告)号：US20200152751A1

公开(公告)日：2020-05-14

申请号：US16687736

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Dechao Guo ,  Tenko Yamashita ,  Veeraraghavan S. Basker ,  Robert Robison ,  Ardasheir Rahman

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/285

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

公开(公告)号：US12268030B2

公开(公告)日：2025-04-01

申请号：US17446784

申请日：2021-09-02

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Robert Robison ,  Hemanth Jagannathan ,  Jay William Strane

IPC: H01L29/66 ,  H10D30/01 ,  H10D30/62 ,  H10D30/63 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

公开(公告)号：US11961759B2

公开(公告)日：2024-04-16

申请号：US17592078

申请日：2022-02-03

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/146 ,  H10N70/00

CPC classification number: H01L21/76807 ,  H01L21/02019 ,  H01L21/02065 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/14636 ,  H10N70/066 ,  H01L2224/80004

Abstract: An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

公开(公告)号：US11854884B2

公开(公告)日：2023-12-26

申请号：US17551531

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53295

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

公开(公告)号：US11791258B2

公开(公告)日：2023-10-17

申请号：US17679719

申请日：2022-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Robert Robison

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5283

Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.