公开(公告)号：US10546787B2

公开(公告)日：2020-01-28

申请号：US15996748

申请日：2018-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Vijay Narayanan ,  Terence B. Hook ,  Hemanth Jagannathan

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/225 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51 ,  H01L21/027 ,  H01L21/311

Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.

公开(公告)号：US20190371676A1

公开(公告)日：2019-12-05

申请号：US15996748

申请日：2018-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Vijay Narayanan ,  Terence B. Hook ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/225 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51

Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.

公开(公告)号：US20190326429A1

公开(公告)日：2019-10-24

申请号：US16502685

申请日：2019-07-03

Applicant: International Business Machines Corporation

Inventor： Devendra Sadana ,  Dechao Guo ,  Joel P. de Souza ,  Ruqiang Bao ,  Stephen w. Bedell ,  Shogo Mochizuki ,  Gen Tsutsui ,  Hemanth Jagannathan ,  Marinus Hopstaken

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/04 ,  H01L21/762

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

公开(公告)号：US10395989B2

公开(公告)日：2019-08-27

申请号：US15788469

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

公开(公告)号：US10381479B2

公开(公告)日：2019-08-13

申请号：US15663133

申请日：2017-07-28

Applicant: International Business Machines Corporation

Inventor： Devendra Sadana ,  Dechao Guo ,  Joel P. de Souza ,  Ruqiang Bao ,  Stephen W. Bedell ,  Shogo Mochizuki ,  Gen Tsutsui ,  Hemanth Jagannathan ,  Marinus Hopstaken

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/04

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

公开(公告)号：US10361130B2

公开(公告)日：2019-07-23

申请号：US15497817

申请日：2017-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Richard G. Southwick

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311 ,  H01L29/10 ,  H01L29/161

Abstract: A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.

公开(公告)号：US10332883B2

公开(公告)日：2019-06-25

申请号：US15826806

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.

公开(公告)号：US10276687B1

公开(公告)日：2019-04-30

申请号：US15848861

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：US10243055B2

公开(公告)日：2019-03-26

申请号：US15908085

申请日：2018-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.

公开(公告)号：US10147725B2

公开(公告)日：2018-12-04

申请号：US14968134

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Gauri Karve ,  Derrick Liu ,  Robert R. Robison ,  Gen Tsutsui ,  Reinaldo A. Vega ,  Koji Watanabe

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02 ,  H01L29/40

Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.