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    Lithographically defined intrinsic identifier
    32.
    发明授权
    Lithographically defined intrinsic identifier 有权

    公开(公告)号：US10778422B2

    公开(公告)日：2020-09-15

    申请号：US15209401

    申请日：2016-07-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Dirk Pfeiffer ,  Sami Rosenblatt ,  Chandrasekara Kothandaraman

    IPC: H04L9/08 ,  G09C1/00

    Abstract: Methods and systems for generating an identifier includes testing an operational characteristic for each device in an array of pairs of devices. Each pair of devices includes a first device and a second device. The first device of each pair has a higher inter-device uniformity for the operational characteristic than the second device of the pair. The operational characteristic between the first device and the second device is compared for each pair of devices to generate a respective identifier bit for each pair of devices. An identifier is generated from the identifier bits.

    Vertical transmon qubit device
    33.
    发明授权
    Vertical transmon qubit device 有权

    公开(公告)号：US10714672B2

    公开(公告)日：2020-07-14

    申请号：US16248141

    申请日：2019-01-15

    Applicant: International Business Machines Corporation

    Inventor： Markus Brink ,  Sami Rosenblatt ,  Rasit Onur Topaloglu

    IPC: H01L39/24 ,  H01L39/22 ,  H01L27/18 ,  G06N10/00 ,  B82Y10/00 ,  B82Y40/00 ,  H01L39/02 ,  H01L29/66

    Abstract: Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

    Providing an authenticating service of a chip
    34.
    发明授权
    Providing an authenticating service of a chip 有权

    公开(公告)号：US10657231B2

    公开(公告)日：2020-05-19

    申请号：US16238738

    申请日：2019-01-03

    Applicant: International Business Machines Corporation

    Inventor： Srivatsan Chellappa ,  Subramanian S. Iyer ,  Toshiaki Kirihata ,  Sami Rosenblatt

    IPC: G06F21/30 ,  G09C1/00 ,  H04L9/32 ,  G06F21/44 ,  G01C1/00 ,  G11B20/00 ,  H04L29/06 ,  H04N1/32

    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

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