公开(公告)号：US10686040B2

公开(公告)日：2020-06-16

申请号：US16395084

申请日：2019-04-25

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L27/088 ,  H01L29/12 ,  H01L29/06 ,  H01L27/085 ,  H01L23/52 ,  H01L21/8234

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20200005848A1

公开(公告)日：2020-01-02

申请号：US16021575

申请日：2018-06-28

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Jin-Ping Han ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC: G11C11/22 ,  G11C11/54 ,  G06F3/06 ,  G06N3/063

Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

公开(公告)号：US20190180185A1

公开(公告)日：2019-06-13

申请号：US15836098

申请日：2017-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xiao Sun ,  Youngseok Kim ,  Chun-Chen Yeh

IPC: G06N3/08 ,  G06F15/80 ,  G06F17/16 ,  G06K9/62 ,  G06F7/58

Abstract: A computer-implemented method for training a random matrix network is presented. The method includes initializing a random matrix, inputting a plurality of first vectors into the random matrix, and outputting a plurality of second vectors from the random matrix to be fed back into the random matrix for training. The random matrix can include a plurality of two-terminal devices or a plurality of three-terminal devices or a film-based device.

公开(公告)号：US20220180171A1

公开(公告)日：2022-06-09

申请号：US17112528

申请日：2020-12-04

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Ankur Agrawal ,  Kailash Gopalakrishnan ,  Naigang Wang ,  Chia-Yu Chen ,  Jiamin Ni

IPC: G06N3/08 ,  G06N3/063 ,  G06F7/499 ,  G06F17/16 ,  G06F7/487

Abstract: An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.

公开(公告)号：US11163533B2

公开(公告)日：2021-11-02

申请号：US16515174

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xiao Sun ,  Ankur Agrawal ,  Kailash Gopalakrishnan ,  Silvia Melitta Mueller ,  Kerstin Claudia Schelm

IPC: G06F7/556 ,  G06F7/523 ,  G06F7/50 ,  G06N3/08

Abstract: A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y′ by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y′ to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.

公开(公告)号：US20210064976A1

公开(公告)日：2021-03-04

申请号：US16558554

申请日：2019-09-03

Applicant: International Business Machines Corporation

Inventor： Xiao Sun ,  Jungwook Choi ,  Naigang Wang ,  Chia-Yu Chen ,  Kailash Gopalakrishnan

IPC: G06N3/063 ,  G06N3/08

Abstract: An apparatus includes circuitry for a neural network that is configured to perform forward propagation neural network operations on floating point numbers having a first n-bit floating point format. The first n-bit floating point format has a configuration consisting of a sign bit, m exponent bits and p mantissa bits where m is greater than p. The circuitry is further configured to perform backward propagation neural network operations on floating point numbers having a second n-bit floating point format that is different than the first n-bit floating point format. The second n-bit floating point format has a configuration consisting of a sign bit, q exponent bits and r mantissa bits where q is greater than m and r is less than p.

公开(公告)号：US10818333B2

公开(公告)日：2020-10-27

申请号：US16550809

申请日：2019-08-26

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC: G11C11/22 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C11/54 ,  G11C16/10 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G11C13/00

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US20200058641A1

公开(公告)日：2020-02-20

申请号：US16662284

申请日：2019-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin-Ping Han ,  Yulong Li ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC: H01L27/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L27/1159 ,  H01L27/11507 ,  H01L21/28

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

公开(公告)号：US10559562B2

公开(公告)日：2020-02-11

申请号：US16360690

申请日：2019-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin-Ping Han ,  Yulong Li ,  Dennis M. Newns ,  Paul M. Solomon ,  Xiao Sun

IPC: H01L27/06 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11507 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

公开(公告)号：US20200013785A1

公开(公告)日：2020-01-09

申请号：US16576441

申请日：2019-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DAVID J. FRANK ,  Paul M. Solomon ,  Xiao Sun

IPC: H01L27/1159 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78

Abstract: A field-effect transistor includes a semiconductor substrate having first, second, third, and fourth sides, and a ferroelectric gate stack on an upper surface of the substrate. The ferroelectric gate stack includes a gate insulating layer; and a ferroelectric material layer on the gate insulating layer. Portions of the upper surface of the substrate between the first side and the ferroelectric gate stack and between the second side and the ferroelectric gate stack are doped with n-type impurities, and portions of the upper surface of the substrate between the third side and the ferroelectric gate stack and between the fourth side and the ferroelectric gate stack are doped with p-type impurities. A presence of both n and p channels in a same region increases a capacitance and voltage gain of the ferroelectric gate stack.