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    Multi-tier trace
    31.
    发明授权
    Multi-tier trace 有权
    多层跟踪

    公开(公告)号：US09164868B2

    公开(公告)日：2015-10-20

    申请号：US13762660

    申请日：2013-02-08

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer

    IPC: G06F11/00 ,  G06F11/34

    CPC classification number: G06F11/3495 ,  G06F11/3024 ,  G06F11/3027 ,  G06F11/3068 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/364 ,  G06F2201/805

    Abstract: The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and systems for a multi-tier trace architecture. A method for separating raw trace data includes receiving raw trace data from one of more CPUs and/or busses in the system, separating the raw trace data into high bandwidth trace information (HBTI) and low bandwidth trace information (LBTI), recording the HBTI on an on-chip trace buffer until a specific event is triggered, and providing in parallel the LBTI over an off-chip trace interface. In one embodiment, the raw trace data are provided to a separate HBTI trace unit and a separate LBTI respectively. The HBTI trace unit processes the HBTI and generates a HBTI message, and the LBTI trace unit processes the LBTI and generates a LBTI message.

    Abstract translation: 本公开涉及计算机处理系统中的跟踪解决方案的方法和系统。 更具体地，本公开涉及用于多层跟踪架构的方法和系统。 用于分离原始迹线数据的方法包括从系统中的多个CPU和/或总线中的一个接收原始跟踪数据，将原始跟踪数据分离成高带宽跟踪信息（HBTI）和低带宽跟踪信息（LBTI），记录HBTI 在片内跟踪缓冲器上，直到触发特定事件，并且通过片外跟踪接口并行提供LBTI。 在一个实施例中，原始跟踪数据分别提供给单独的HBTI跟踪单元和单独的LBTI。 HBTI跟踪单元处理HBTI并生成HBTI消息，LBTI跟踪单元处理LBTI并生成LBTI消息。

    TOOL SECURITY SYSTEM
    32.
    发明申请
    TOOL SECURITY SYSTEM 有权

    公开(公告)号：US20240403497A1

    公开(公告)日：2024-12-05

    申请号：US18327909

    申请日：2023-06-02

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer ,  Gasper Skvarc Bozic

    IPC: G06F21/85 ,  H04L12/40

    Abstract: Systems, methods, and circuitries are disclosed for providing security for tool access in a device. In one example, a device includes a bus master, a memory protection unit, and protection agent circuitry. The bus master is configured to store, in a first range of memory locations, request messages received from a tool interface of the device, each request message encapsulating a tool-related command. The memory protection unit is configured to prevent the bus master from accessing memory locations outside of the first range of memory locations. The protection agent circuitry is configured to access the first range of memory locations to identify one or more request messages, and send each respective request message to one of a plurality of component circuitries based on a component circuitry identified by the request message.

    SYSTEMS, DEVICES, AND METHODS FOR CONNECTORS
    33.
    发明公开
    SYSTEMS, DEVICES, AND METHODS FOR CONNECTORS 审中-公开

    公开(公告)号：US20240322499A1

    公开(公告)日：2024-09-26

    申请号：US18732874

    申请日：2024-06-04

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer ,  Patrik Eder

    IPC: H01R13/66 ,  G06F13/40

    CPC classification number: H01R13/665 ,  G06F13/4081

    Abstract: A circuit is disclosed having one or more circuits, a connector portion coupled to the one or more circuits, and comprising a plurality of pins. When the connector portion is coupled with a first connector in a first orientation, the one or more circuits are configured to operate in a first state, and when the connector portion is coupled with the first connector in a second orientation, at least one pin of the plurality of pins receives a signal causing the one or more circuits to operate in a second state different from the first state. The second orientation being different from the first orientation.

    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION
    35.
    发明公开
    SYSTEMS, DEVICES, AND METHODS FOR DYNAMIC ALLOCATION 审中-公开

    公开(公告)号：US20230161862A1

    公开(公告)日：2023-05-25

    申请号：US17981583

    申请日：2022-11-07

    Applicant: Infineon Technologies AG

    Inventor： Sandeep Vangipuram ,  Glenn Farrall ,  Albrecht Mayer ,  Frank Hellwig

    IPC: G06F21/44

    CPC classification number: G06F21/44

    Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

    Resource protection
    36.
    发明授权
    Resource protection 有权

    公开(公告)号：US11288404B2

    公开(公告)日：2022-03-29

    申请号：US16441227

    申请日：2019-06-14

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer ,  Glenn Ashley Farrall ,  Frank Hellwig

    IPC: G06F21/74

    Abstract: A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

    CONTROL SYSTEM AND METHOD OF MEMORY ACCESS
    38.
    发明申请
    CONTROL SYSTEM AND METHOD OF MEMORY ACCESS 审中-公开

    公开(公告)号：US20180300144A1

    公开(公告)日：2018-10-18

    申请号：US15945114

    申请日：2018-04-04

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer ,  Glenn Ashley Farrall

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.

    Lightweight trace based measurement systems and methods
    39.
    发明授权
    Lightweight trace based measurement systems and methods 有权

    公开(公告)号：US10042738B2

    公开(公告)日：2018-08-07

    申请号：US15712536

    申请日：2017-09-22

    Applicant: Infineon Technologies AG

    Inventor： Albrecht Mayer

    IPC: G06F11/34 ,  G06F11/36

    Abstract: An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit.

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