公开(公告)号：US09472395B2

公开(公告)日：2016-10-18

申请号：US14594838

申请日：2015-01-12

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder

IPC: H01L21/02 ,  H01L21/74 ,  H01L21/225

CPC classification number: H01L21/02258 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/74 ,  H01L21/78

Abstract: In accordance with a method of manufacturing a semiconductor arrangement, a first trench is formed into a semiconductor body from a first side. An anodic oxide structure is formed at a bottom side of the first trench by immersing the semiconductor body in an electrolyte and applying an anodizing voltage between the semiconductor body and an electrode in contact with the electrolyte.

Abstract translation: 根据制造半导体装置的方法，从第一侧将第一沟槽形成为半导体本体。 通过将半导体本体浸入电解质中并在半导体本体和与电解质接触的电极之间施加阳极氧化电压，在第一沟槽的底侧形成阳极氧化物结构。

公开(公告)号：US20220310380A1

公开(公告)日：2022-09-29

申请号：US17841781

申请日：2022-06-16

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US11373857B2

公开(公告)日：2022-06-28

申请号：US16411784

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Iris Moder ,  Petra Fischer

IPC: H01L21/02 ,  H01L29/16 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/304 ,  H01L21/3065

Abstract: One or more semiconductor manufacturing methods and/or semiconductor arrangements are provided. In an embodiment, a silicon carbide (SiC) layer is provided. The SiC layer has a first portion overlying a second portion. The first portion has a first side distal the second portion and a second side proximal the second portion. The first portion is converted into a porous layer overlying the second portion. The porous layer has a first side distal the second portion and a second side proximal the second portion. The porous layer is removed to expose a first side of the second portion. After removing the porous layer, the first side of the second portion has a surface roughness less than a surface roughness of the first side of the first portion and/or less than a surface roughness of the first side of the porous layer.

公开(公告)号：US20210391377A1

公开(公告)日：2021-12-16

申请号：US17345534

申请日：2021-06-11

Applicant: Infineon Technologies AG

Inventor： Alexander Frey ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri ,  Alfred Sigl ,  Tobias Weindler

IPC: H01L27/146 ,  H01L23/544 ,  H01L21/304 ,  H01L29/78 ,  G01S17/894

Abstract: A method of manufacturing a semiconductor device is described. The method includes providing a semiconductor substrate. The semiconductor substrate includes a high-doped semiconductor substrate layer, a high-doped semiconductor device layer, and a low-doped semiconductor etch stop layer arranged between the high-doped semiconductor substrate layer and the high-doped semiconductor device layer. The high-doped semiconductor substrate layer is removed, wherein the removing includes dopant selective chemical etching stopping at the low-doped semiconductor etch stop layer. Further, the low-doped semiconductor etch stop layer is thinned to generate an exposed surface of the high-doped semiconductor device layer.

公开(公告)号：US20210391218A1

公开(公告)日：2021-12-16

申请号：US17343885

申请日：2021-06-10

Applicant: Infineon Technologies AG

Inventor： Felix Johannes Heinrich Ernst ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/225 ,  H01L29/06 ,  H01L23/14

Abstract: A method of manufacturing a semiconductor device is described. A semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate layer and a semiconductor device layer. The method includes transforming areas of the semiconductor device layer into dicing areas which can be removed by etching, and removing the semiconductor substrate layer and the dicing areas by using etching.

公开(公告)号：US10714377B2

公开(公告)日：2020-07-14

申请号：US16122456

申请日：2018-09-05

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Bernhard Goller ,  Iris Moder ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/861 ,  H01L21/306 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L29/32 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L21/266 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

公开(公告)号：US20200176580A1

公开(公告)日：2020-06-04

申请号：US16693909

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Iris Moder ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Carsten von Koblinski

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66

Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.

公开(公告)号：US20190074212A1

公开(公告)日：2019-03-07

申请号：US16122456

申请日：2018-09-05

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Bernhard Goller ,  Iris Moder ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/66 ,  H01L21/02 ,  H01L29/06 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

公开(公告)号：US20180374843A1

公开(公告)日：2018-12-27

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

公开(公告)号：US10049914B2

公开(公告)日：2018-08-14

申请号：US14946886

申请日：2015-11-20

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Hans-Joachim Schulze ,  Francisco Javier Santos Rodriguez ,  Iris Moder ,  Ingo Muri

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.