公开(公告)号：US11756923B2

公开(公告)日：2023-09-12

申请号：US17464113

申请日：2021-09-01

Applicant: Infineon Technologies AG

Inventor： Marian Sebastian Broll ,  Barbara Eichinger ,  Alexander Herbrandt ,  Alparslan Takkac

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/84 ,  H01L24/05 ,  H01L24/40 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/05766 ,  H01L2224/05787 ,  H01L2224/40245 ,  H01L2224/84214 ,  H01L2224/84238 ,  H01L2224/84379

Abstract: A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

公开(公告)号：US20230063259A1

公开(公告)日：2023-03-02

申请号：US17464113

申请日：2021-09-01

Applicant: Infineon Technologies AG

Inventor： Marian Sebastian Broll ,  Barbara Eichinger ,  Alexander Herbrandt ,  Alparslan Takkac

IPC: H01L23/00

Abstract: A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

公开(公告)号：US09929111B2

公开(公告)日：2018-03-27

申请号：US15461500

申请日：2017-03-17

Applicant: Infineon Technologies AG

Inventor： Martin Mischitz ,  Markus Heinrici ,  Barbara Eichinger ,  Manfred Schneegans ,  Stefan Krivec

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L23/532 ,  H01L21/762

CPC classification number: H01L24/03 ,  H01L21/02203 ,  H01L21/02513 ,  H01L21/76259 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/0331 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.

公开(公告)号：US11329021B2

公开(公告)日：2022-05-10

申请号：US16685318

申请日：2019-11-15

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Fabian Craes ,  Barbara Eichinger ,  Martin Mischitz ,  Frederik Otto ,  Fabien Thion

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/428 ,  H01L21/782

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

公开(公告)号：US20210098410A1

公开(公告)日：2021-04-01

申请号：US17060434

申请日：2020-10-01

Applicant: Infineon Technologies AG

Inventor： Ali Roshanghias ,  Alfred Binder ,  Barbara Eichinger ,  Stefan Karner ,  Martin Mischitz ,  Rainer Pelzer

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

公开(公告)号：US10199372B2

公开(公告)日：2019-02-05

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

公开(公告)号：US11552048B2

公开(公告)日：2023-01-10

申请号：US17101339

申请日：2020-11-23

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Barbara Eichinger ,  Thorsten Meyer ,  Ingo Muri

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

公开(公告)号：US11488921B2

公开(公告)日：2022-11-01

申请号：US17060434

申请日：2020-10-01

Applicant: Infineon Technologies AG

Inventor： Ali Roshanghias ,  Alfred Binder ,  Barbara Eichinger ,  Stefan Karner ,  Martin Mischitz ,  Rainer Pelzer

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

公开(公告)号：US20200161269A1

公开(公告)日：2020-05-21

申请号：US16685318

申请日：2019-11-15

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Fabian Craes ,  Barbara Eichinger ,  Martin Mischitz ,  Frederik Otto ,  Fabien Thion

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/428

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

公开(公告)号：US20180374843A1

公开(公告)日：2018-12-27

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.