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公开(公告)号：US20170271722A1
公开(公告)日：2017-09-21
申请号：US15463265
申请日：2017-03-20
摘要： A semiconductor battery includes a substrate, a battery anode semiconductor material arranged in or over the substrate, a battery cathode material arranged in or over the substrate and a battery electrolyte disposed between the battery anode semiconductor material and the battery cathode material. An electrically insulating encapsulant has a first face and a second face. The substrate is at least partly embedded in the encapsulant. An anode electrode is electrically connected to the battery anode semiconductor material and is disposed over the second face of the encapsulant. A cathode electrode is electrically connected to the battery cathode material and is disposed over the first face of the encapsulant.
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公开(公告)号：US20170012110A1
公开(公告)日：2017-01-12
申请号：US15205323
申请日：2016-07-08
发明人： Rolf Weis , Martin Bartels , Marko Lemke , Stefan Tegen
IPC分类号： H01L29/66 , H01L21/28 , H01L29/10 , H01L29/739 , H01L29/423
CPC分类号： H01L29/66348 , H01L29/1095 , H01L29/407 , H01L29/7397 , H01L29/7398
摘要： A method includes forming a first trench in a semiconductor body between two semiconductor fins, filling the first trench with a first filling material, partially removing the first filling material by forming a second trench such that the second trench has a lower aspect ratio than the first trench, and at least partially filling the second trench with a second filling material so as to form a continuous material layer on the first filling material. A semiconductor device includes a first trench in a semiconductor body between two semiconductor fins, the first trench being filled with a first filling material, and a second trench having a lower aspect ratio than the first trench and being at least partially filled with a second filling material which forms a continuous material layer on the first filling material.
摘要翻译： 一种方法包括在半导体本体之间在两个半导体鳍片之间形成第一沟槽，用第一填充材料填充第一沟槽，通过形成第二沟槽部分地去除第一填充材料，使得第二沟槽具有比第一沟槽更低的纵横比 沟槽，并且用第二填充材料至少部分地填充第二沟槽，以便在第一填充材料上形成连续的材料层。 半导体器件包括半导体本体中的两个半导体鳍片之间的第一沟槽，第一沟槽填充有第一填充材料，第二沟槽具有比第一沟槽更低的纵横比，并且至少部分地填充有第二填充物 在第一填充材料上形成连续材料层的材料。
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33.发明申请Transistor Arrangement Including Power Transistors and Voltage Limiting Means 审中-公开晶体管布置包括功率晶体管和限压装置公开(公告)号：US20160343848A1
公开(公告)日：2016-11-24
申请号：US15158126
申请日：2016-05-18
发明人： Martin Bartels , Marko Lemke , Ralf Rudolf , Stefan Tegen , Rolf Weis
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L27/06 , H01L29/40 , H01L29/739 , H01L29/866 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7808 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/4236 , H01L29/7397 , H01L29/7805 , H01L29/7809 , H01L29/781 , H01L29/7811 , H01L29/7813
摘要： A Transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer.
摘要翻译： 半导体主体中的晶体管布置包括具有至少两个晶体管单元的功率晶体管，每个晶体管单元布置在半导体本体的半导体鳍片中，并具有至少两个器件单元的电压限制器件。 每个器件单元被布置在相应晶体管单元的半导体鳍中的晶体管单元附近，并且电压限制器件通过电介质层与功率晶体管分离。
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公开(公告)号：US09318550B2
公开(公告)日：2016-04-19
申请号：US14625796
申请日：2015-02-19
发明人： Marko Lemke , Rolf Weis , Stefan Tegen
IPC分类号： H01L21/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/06 , H01L21/762 , H01L29/78 , H01L29/423 , H01L21/8234 , H01L27/088 , H01L27/02
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/76224 , H01L21/76232 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L29/4236 , H01L29/66795 , H01L29/7813 , H01L29/7827 , H01L29/7851
摘要： A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.
摘要翻译： 半导体器件包括第一栅电极结构，第二栅电极结构，器件分离结构和电池分离结构。 第一栅极电极结构被埋在与半导体部分的第一表面相距一定距离的第一单元阵列的半导体部分中。 第一栅电极结构包括平行阵列条纹。 第二栅极电极结构被埋在与第一单元阵列相邻的第二单元阵列中的半导体部分中。 第二栅电极结构包括平行阵列条纹。 器件分离结构在第一和第二电池阵列之间。 装置分离结构具有第一宽度。 细胞分离结构具有至少第二宽度小于第一宽度的第二宽度，并且在第一表面处切口由阵列沟槽之间的半导体部分的部分形成。
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公开(公告)号：US20150179736A1
公开(公告)日：2015-06-25
申请号：US14625796
申请日：2015-02-19
发明人： Marko Lemke , Rolf Weis , Stefan Tegen
IPC分类号： H01L29/06 , H01L29/78 , H01L29/423 , H01L27/088
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/76224 , H01L21/76232 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L29/4236 , H01L29/66795 , H01L29/7813 , H01L29/7827 , H01L29/7851
摘要： A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.
摘要翻译： 半导体器件包括第一栅电极结构，第二栅电极结构，器件分离结构和电池分离结构。 第一栅极电极结构被埋在与半导体部分的第一表面相距一定距离的第一单元阵列的半导体部分中。 第一栅电极结构包括平行阵列条纹。 第二栅极电极结构被埋在与第一单元阵列相邻的第二单元阵列中的半导体部分中。 第二栅电极结构包括平行阵列条纹。 器件分离结构在第一和第二电池阵列之间。 装置分离结构具有第一宽度。 细胞分离结构具有至少第二宽度小于第一宽度的第二宽度，并且在第一表面处切口由阵列沟槽之间的半导体部分的部分形成。
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36.发明授权Apparatus, storage device, switch and methods, which include microstructures extending from a support 有权装置，存储装置，开关和方法，其包括从支撑件延伸的微结构公开(公告)号：US09047985B2
公开(公告)日：2015-06-02
申请号：US13656631
申请日：2012-10-19
发明人： Marko Lemke , Stefan Tegen
CPC分类号： G11C23/00 , B82Y10/00 , G11C13/025
摘要： An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other.
摘要翻译： 一种装置具有从支撑件延伸的支撑件和多个可弯曲和导电的微结构。 多个微结构的两个相邻微结构如果它们没有被弯曲，则其可以确定可检测的第一状态，使得其相对于支撑件远端的端部不彼此接触，并且多个微结构中的两个相邻微结构限定 如果它们被弯曲使得其相对于支撑件远端的端部彼此接触并彼此固定，则可检测的第二状态。
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37.发明授权Method of manufacturing a semiconductor device with device separation structures 有权制造具有器件分离结构的半导体器件的方法公开(公告)号：US08987090B2
公开(公告)日：2015-03-24
申请号：US13935038
申请日：2013-07-03
发明人： Marko Lemke , Rolf Weis , Stefan Tegen
IPC分类号： H01L21/336 , H01L29/78 , H01L21/762
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/76224 , H01L21/76232 , H01L21/764 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/0883 , H01L27/0886 , H01L29/4236 , H01L29/66795 , H01L29/7813 , H01L29/7827 , H01L29/7851
摘要： A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern including array trenches from a first surface into a semiconductor substrate, wherein an array isolation portion of the semiconductor substrate separates the first and second trench patterns. A buried gate electrode structure is provided in the first and second trench patterns at a distance to the first surface. In a single etch process, both a device separation trench having a first width is introduced into the array isolation portion and cell separation trenches having at most a second width that is smaller than the first width are introduced into semiconductor fins between the array trenches. Switching devices integrated in the same semiconductor die may be formed in a cost effective way.
摘要翻译： 一种制造半导体器件的方法包括将包括阵列沟槽的至少第一和第二沟槽图案从第一表面引入到半导体衬底中，其中半导体衬底的阵列隔离部分分离第一和第二沟槽图案。 掩模栅电极结构设置在第一和第二沟槽图案中与第一表面相距一定距离处。 在单个蚀刻工艺中，将具有第一宽度的器件分离沟槽引入阵列隔离部分，并且具有至少第二宽度小于第一宽度的细胞分离沟槽被引入到阵列沟槽之间的半导体鳍片中。 集成在同一半导体管芯中的开关器件可以以成本有效的方式形成。
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公开(公告)号：US20140134844A1
公开(公告)日：2014-05-15
申请号：US13674136
申请日：2012-11-12
发明人： Stefan Tegen , Marko Lemke
IPC分类号： H01L21/308
CPC分类号： H01L21/308 , H01L21/823431 , H01L21/845
摘要： In various embodiments, a method for processing a die is provided. The method may include forming a periodic structure at least one of over and in a carrier, the periodic structure including a plurality of structure elements; depositing masking material over the periodic structure; partially removing masking material to expose at least one structure element but not all of the structure elements; and removing the exposed at least one structure element.
摘要翻译： 在各种实施例中，提供了一种用于处理模具的方法。 该方法可以包括形成在载体中和载体中至少一个的周期性结构，所述周期结构包括多个结构元件; 在周期性结构上沉积掩模材料; 部分去除掩模材料以暴露至少一个结构元件，但不是全部结构元件; 以及去除暴露的至少一个结构元件。
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