公开(公告)号：US20190065426A1

公开(公告)日：2019-02-28

申请号：US16171342

申请日：2018-10-25

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC分类号： G06F13/40 ,  G06F13/42

摘要： Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20190065272A1

公开(公告)日：2019-02-28

申请号：US15682896

申请日：2017-08-22

申请人： Intel Corporation

发明人： Anil Rao ,  Debendra Das Sharma

IPC分类号： G06F9/50 ,  G06F9/48 ,  G06F9/44 ,  H04L29/08

摘要： The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

公开(公告)号：US20180267850A1

公开(公告)日：2018-09-20

申请号：US15761405

申请日：2015-09-26

申请人： Intel Corporation

发明人： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC分类号： G06F11/08 ,  G06F11/22 ,  G06F13/14 ,  H04L1/00

CPC分类号： G06F11/08 ,  G06F11/1004 ,  G06F11/221 ,  G06F13/14 ,  H04L1/0061

摘要： There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

公开(公告)号：US10019300B2

公开(公告)日：2018-07-10

申请号：US15042463

申请日：2016-02-12

申请人： Intel Corporation

发明人： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14

CPC分类号： G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

摘要： A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

公开(公告)号：US20170371831A1

公开(公告)日：2017-12-28

申请号：US15193941

申请日：2016-06-27

申请人： Intel Corporation

发明人： Debendra Das Sharma

IPC分类号： G06F13/42 ,  G06F13/40

CPC分类号： G06F13/4291 ,  G06F13/4068

摘要： A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

公开(公告)号：US09626321B2

公开(公告)日：2017-04-18

申请号：US14060191

申请日：2013-10-22

申请人： Intel Corporation

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： G06F13/40 ,  G06F12/0831 ,  G06F13/42 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0815 ,  H04L12/741 ,  G06F9/44

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

公开(公告)号：US09552253B2

公开(公告)日：2017-01-24

申请号：US14495797

申请日：2014-09-24

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  Robert G. Blankenship ,  Debendra Das Sharma

IPC分类号： G06F11/00 ,  G06F11/10 ,  H04L1/00 ,  G06F13/42

CPC分类号： G06F11/1004 ,  G06F13/4221 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L2001/0096

摘要： A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic redundancy check (CRC) value of the flit. The link includes a plurality of lanes. It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes.

摘要翻译： 确定通过链路发送的飞行中的位错误被确定为基于与飞行的循环冗余校验（CRC）值相关联的校正子值来影响飞行的一个或多个特定比特。 该链路包括多个车道。 确定一个或多个特定位在链路的一个或多个特定通道上发送。 基于确定受影响的位在特定车道上传送，位错误与一个或多个特定车道相关联。

公开(公告)号：US20160377679A1

公开(公告)日：2016-12-29

申请号：US15039515

申请日：2013-12-26

申请人： INTEL CORPORATION

发明人： Daniel S. Froelich ,  Debendra Das Sharma

IPC分类号： G01R31/317 ,  G01R31/3177

摘要： A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

摘要翻译： 生成测试模式信号以包括测试模式和错误报告序列。 测试模式信号在包括一个或多个扩展设备和两个或更多个子链接的链路上发送。 测试模式信号将被发送在特定的一个子链路上，并且由接收设备使用以识别特定子链路上的错误。 错误报告序列将用错误信息进行编码，以描述多个子链接中的子链接的错误状态。

公开(公告)号：US09355058B2

公开(公告)日：2016-05-31

申请号：US13976937

申请日：2013-03-27

申请人： Intel Corporation

发明人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

IPC分类号： G06F13/42 ,  G06N99/00

CPC分类号： G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

摘要： A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

公开(公告)号：US09262270B2

公开(公告)日：2016-02-16

申请号：US13892894

申请日：2013-05-13

申请人： Intel Corporation

发明人： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC分类号： G06F11/16 ,  G06F11/14 ,  G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

摘要： A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

摘要翻译： 在串行数据链路的端口处识别分组，并且确定分组与错误相关联。 基于确定该分组与该错误相关联来进入错误恢复模式。 进入错误恢复模式可能导致串行数据链路被强制关闭。 在一个方面，强制数据链路断开导致所有后续入站分组被丢弃，并且所有待处理的出站请求和完成将在错误恢复模式期间中止。