公开(公告)号：US12288744B2

公开(公告)日：2025-04-29

申请号：US17742816

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown ,  Cheng Xu ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US20240421043A1

公开(公告)日：2024-12-19

申请号：US18211455

申请日：2023-06-19

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Ji Yong Park ,  Kyu Oh Lee ,  Sheng Li ,  Gang Duan ,  Sameer Paital

IPC: H01L23/495 ,  H01L21/768

Abstract: Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.

公开(公告)号：US11735537B2

公开(公告)日：2023-08-22

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20200373257A1

公开(公告)日：2020-11-26

申请号：US16990782

申请日：2020-08-11

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US10777514B2

公开(公告)日：2020-09-15

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01F27/24 ,  H01L27/04 ,  H01F27/28 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20190355654A1

公开(公告)日：2019-11-21

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US10384431B2

公开(公告)日：2019-08-20

申请号：US15475157

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Sri Chaitra J. Chavali ,  Siddharth K. Alur ,  Kyu Oh Lee

IPC: B32B37/10 ,  H05K3/46 ,  H05K3/00 ,  B32B37/06 ,  H05K3/02

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.

公开(公告)号：US10373951B1

公开(公告)日：2019-08-06

申请号：US16017247

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Rahul Jain ,  Seo Young Kim ,  Kyu Oh Lee ,  Ji Yong Park ,  Sai Vadlamani ,  Junnan Zhao

IPC: H01L27/07 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：US20180286812A1

公开(公告)日：2018-10-04

申请号：US15475175

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.