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公开(公告)号：US10725929B2
公开(公告)日：2020-07-28
申请号：US15483741
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Jianfang Zhu , Cristiano J. Ferreira , Bo Qiu , Ajit Krisshna Nandyal Lakshman , Nikhil Talpallikar , Deepak Gandiga Shivakumar , Brandt M. Guttridge , Kim Pallister , Frank J. Soqui , Anand Srivatsa , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jonathan Kennedy
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F12/10 , G06F12/0875 , G06F12/0811 , G06T1/60 , G06F3/06 , G06F12/06 , G06F12/02 , G06F12/109
Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.
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32.发明申请公开(公告)号：US20200074714A1
公开(公告)日：2020-03-05
申请号：US16566989
申请日：2019-09-11
Applicant: Intel Corporation
Inventor： Michael Apodaca , Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Abhishek Venkatesh , Jonathan Kennedy , Slawomir Grajewski
Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.
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33.发明申请公开(公告)号：US20190287290A1
公开(公告)日：2019-09-19
申请号：US16271368
申请日：2019-02-08
Applicant: Intel Corporation
Inventor： Chandrasekaran Sakthivel , Michael Apodaca , Kai Xiao , Altug Koker , Jeffery S. Boles , Adam T. Lake , Nikos Kaburlasos , Joydeep Ray , John H. Feit , Travis T. Schluessler , Jacek Kwiatkowski , James M. Holland , Prasoonkumar Surti , Jonathan Kennedy , Louis Feng , Barnan Das , Narayan Biswal , Stanley J. Baran , Gokcen Cilingir , Nilesh V. Shah , Archie Sharma , Mayuresh M. Varerkar
Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.
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公开(公告)号：US10347357B2
公开(公告)日：2019-07-09
申请号：US15495143
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Altug Koker , Travis T. Schluessler , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Jonathan Kennedy
Abstract: Systems, apparatuses and methods provide for technology that identifies a redundant portion of a packaged on-die memory and detects, during a field test of the packaged on-die memory, one or more failed cells in the packaged on-die memory. Additionally, the technology identifies whether the redundant portion includes one or more remaining memory cells, and in response to an identification that the redundant portion includes the one or more remaining memory cells, the one or more remaining memory cells in the redundant portion are substituted for the one or more failed memory cells.
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公开(公告)号：US20180307984A1
公开(公告)日：2018-10-25
申请号：US15494971
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kamal Sinha , Joydeep Ray , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Anbang Yao , Kevin Nealis , Xiaoming Chen , John C. Weast , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Farshad Akhbari , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy , Vasanth Ranganathan , Sanjeev Jahagirdar
CPC classification number: G06N3/08 , G06F9/28 , G06F9/505 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N99/005
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20180307295A1
公开(公告)日：2018-10-25
申请号：US15493243
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Mohammed Tameem , Altug Koker , Kiran C. Veernapu , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Travis T. Schluessler , Jonathan Kennedy
Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
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37.发明申请公开(公告)号：US20180300930A1
公开(公告)日：2018-10-18
申请号：US15488824
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Jonathan Kennedy , Gabor Liktor , Jeffery S. Boles , Slawomir Grajewski , Balaji Vembu , Travis T. Schluessler , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , Altug Koker , Jacek Kwiatkowski
CPC classification number: G06T15/005 , A63F13/53 , A63F2300/303 , A63F2300/66
Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.
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38.发明申请公开(公告)号：US20180286106A1
公开(公告)日：2018-10-04
申请号：US15477028
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Michael Apodaca , Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Abhishek Venkatesh , Jonathan Kennedy , Slawomir Grajewski
Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.
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公开(公告)号：US20180284868A1
公开(公告)日：2018-10-04
申请号：US15477029
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：US12229871B2
公开(公告)日：2025-02-18
申请号：US17481656
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer K P , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
IPC: G06T15/08 , G02B27/01 , G06T15/00 , G06T15/10 , G06T15/60 , G06V20/40 , G06V40/19 , H04N13/239 , H04N13/344 , H04N23/67 , H04N25/702
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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