公开(公告)号：US20220095456A1

公开(公告)日：2022-03-24

申请号：US17543311

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Arumanayagam Rajasekar ,  Tin Poay Chuah ,  Sushil Padmanabhan ,  Aiswarya M. Pious ,  Navneet Kumar Singh

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/14

Abstract: In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.

公开(公告)号：US11178768B2

公开(公告)日：2021-11-16

申请号：US15089303

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

IPC: H05K1/18 ,  H05K1/14 ,  H01L25/18 ,  G06K9/00 ,  H05K1/02 ,  H05K9/00 ,  H05K3/36

Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.

公开(公告)号：US11006514B2

公开(公告)日：2021-05-11

申请号：US16481043

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Jia Yan Go ,  Min Suet Lim ,  Tin Poay Chuah ,  Seok Ling Lim ,  Howe Yin Loo

IPC: H01L23/552 ,  H05K1/02 ,  H01L21/50 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H01L49/02 ,  H01L23/64

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

公开(公告)号：US10701796B2

公开(公告)日：2020-06-30

申请号：US16016997

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Yew San Lim ,  Khai Ern Ke See ,  Khang Choong Yong ,  Kevin J. Byrd

IPC: H05K9/00 ,  H05K1/02 ,  G06F1/18 ,  H01L23/552 ,  G06F1/16 ,  H05K3/46

Abstract: In embodiments, a device may include a single electromagnetic interference (EMI) shield plate that defines an enclosed area. The EMI shield plate may have an inner surface and an outer surface opposite the inner surface. The device may further include a first printed circuit board (PCB) coupled with the inner surface, wherein the first PCB is within the enclosed area. Other embodiments may be described and/or claimed.

公开(公告)号：US20190364702A1

公开(公告)日：2019-11-28

申请号：US16535766

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC: H05K9/00 ,  H05K1/11 ,  H05K3/46

Abstract: Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20190342996A1

公开(公告)日：2019-11-07

申请号：US16513004

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

IPC: H05K1/11 ,  H05K1/14

Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

公开(公告)号：US20190045621A1

公开(公告)日：2019-02-07

申请号：US16016997

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Yew San Lim ,  Khai Ern Ke See ,  Khang Choong Yong ,  Kevin J. Byrd

IPC: H05K1/02 ,  H05K9/00 ,  H01L23/552 ,  G06F1/18

Abstract: In embodiments, a device may include a single electromagnetic interference (EMI) shield plate that defines an enclosed area. The EMI shield plate may have an inner surface and an outer surface opposite the inner surface. The device may further include a first printed circuit board (PCB) coupled with the inner surface, wherein the first PCB is within the enclosed area. Other embodiments may be described and/or claimed.

公开(公告)号：US11942412B2

公开(公告)日：2024-03-26

申请号：US17069421

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36 ,  H05K3/46

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L23/5387 ,  H05K1/144 ,  H05K1/147 ,  H05K1/189 ,  H05K3/361 ,  H05K3/4697 ,  H05K2201/10378

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

公开(公告)号：US20230017925A1

公开(公告)日：2023-01-19

申请号：US17946808

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim ,  Twan Sing Loo

IPC: H05K1/02 ,  H05K7/20 ,  G06F1/20

Abstract: Circuit apparatus are disclosed. An example circuit apparatus includes a body including a plurality of first traces formed on the body, and a plurality of openings formed through the body and located between respective ones of the first traces. The openings provide airflow to a fan module of an electronic device through the body of the circuit apparatus.

公开(公告)号：US11556157B2

公开(公告)日：2023-01-17

申请号：US17089752

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Chee Chun Yee ,  Yew San Lim ,  Jeff Ku ,  Tin Poay Chuah

IPC: G06F1/20 ,  H05K7/20 ,  G06F1/16

Abstract: According to the present disclosure, a laptop may be provided with a smaller z-height using a motherboard assembly, including a motherboard having a plurality of components coupled thereon, a thermal transfer unit coupled to one or more component on the motherboard and attachment members for holding the motherboard in a lower compartment of a laptop clamshell casing at an inclining position.