公开(公告)号：US09082927B1

公开(公告)日：2015-07-14

申请号：US14137640

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Dipankar Pramanik ,  Frank Greer ,  Andrew Steinbach

IPC: H01L39/00 ,  H01L39/24 ,  C23C16/455 ,  C23C14/34 ,  H01L39/22 ,  C23C14/08

CPC classification number: H01L39/2493 ,  C23C14/083 ,  C23C14/34 ,  C23C16/45525 ,  H01L39/223

Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (

Abstract translation: 在超导装置（例如约瑟夫逊结）中的隧道阻挡层由催化生长的二氧化硅在低温（<100℃，例如20-30℃）下制成，其不容易在超导电极处形成氧化或硅化物 接口。 隧道势垒开始于沉积在超导电极上并被薄的氧可渗透催化层覆盖的硅层。 氧气在与催化层接触时解离，所得到的氧原子通过催化层，氧化下面的硅。 当所有硅转化为二氧化硅时，反应自限制。

公开(公告)号：US20150179918A1

公开(公告)日：2015-06-25

申请号：US14138672

申请日：2013-12-23

Applicant: Intermolecular Inc.

Inventor： Frank Greer ,  Andy Steinbach

IPC: H01L39/24

CPC classification number: H01L39/2493

Abstract: In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.

Abstract translation: 在用于约瑟夫逊结制造的“窗口”形成工艺中，在第一超导电极层上形成间隔电介质，然后形成开口（“窗口”形成以露出用于结的电极层的部分 在具有直接或远程等离子体能力的原子层沉积（ALD）腔室（或多室密封系统）中，用Ar，H2或组合对暴露的电极部分进行溅射蚀刻，以去除天然氧化物，蚀刻 残留物和其他污染物，任选地，可以在溅射蚀刻之前进行O 2或O 3预清洁。当电极清洁时，隧道势垒层由原位沉积而不进一步氧化剂暴露。

公开(公告)号：US20150179915A1

公开(公告)日：2015-06-25

申请号：US14138909

申请日：2013-12-23

Applicant: INTERMOLECULAR, INC.

Inventor： Frank Greer ,  Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach

IPC: H01L39/24 ,  C23C16/24 ,  C23C16/50 ,  H01L39/12

CPC classification number: C23C16/50 ,  C23C16/24 ,  C23C16/56 ,  H01L21/02123 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76891 ,  H01L23/53285 ,  H01L23/5329 ,  H01L27/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.

Abstract translation: 制造用于超导电子器件（例如，非晶硅，氧化硅或氮化硅）的电介质，通过在整个整个层中的氟钝化降低损耗角正切。 将荧光（气体或等离子体）连续地或作为一系列脉冲注入到处理室中，同时电介质通过化学气相沉积在衬底上形成。 为了进一步减少缺陷，可以从包括多个共键合的硅原子的硅前体（例如乙硅烷或丙硅烷）沉积硅。

公开(公告)号：US20150179436A1

公开(公告)日：2015-06-25

申请号：US14139222

申请日：2013-12-23

Applicant: Intermolecular Inc.

Inventor： Frank Greer ,  Andy Steinbach ,  Wenxian Zhu

IPC: H01L21/02

CPC classification number: H01L27/18 ,  H01L39/2493

Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.

公开(公告)号：US20150140834A1

公开(公告)日：2015-05-21

申请号：US14083124

申请日：2013-11-18

Applicant: Intermolecular Inc.

Inventor： Kevin Kashefi ,  Frank Greer

IPC: H01L21/02 ,  H01L29/51

CPC classification number: H01L21/02304 ,  H01L21/02046 ,  H01L21/02181 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/28194 ,  H01L29/517

Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.

Abstract translation: 公开了使用等离子体源处理半导体表面的方法和装置。 该装置包括封闭衬底支撑件的外部真空室，等离子体源（直接等离子体或远程等离子体）和可选的喷头。 也可以使用其他气体分配和气体分散硬件。 等离子体源可用于产生可操作以改变半导体材料的表面的活化物质。 此外，等离子体源可以用于产生可操作以增强半导体表面上的沉积前体的成核的活化物质。

公开(公告)号：US08975706B2

公开(公告)日：2015-03-10

申请号：US14135381

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28158 ,  H01L21/0215 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.

Abstract translation: 提供场效应晶体管（FET）组件及其形成方法。 FET组件可以包括由钽氧化硅形成并且具有小于5％的硅与钽和硅（Si /（Ta + Si））的原子比的介电层以提供低陷阱密度。 电介质层可以设置在界面层上，该界面层设置在沟道区域上。 可以使用相同类型的电介质层的nMOSFET（例如，III-V材料）和pMOSFET（例如，锗）的公共栅极电介质。 沟道区可以包括砷化铟镓，磷酸铟或锗中的一种。 界面层可以包括氧化硅以提供更高的能量势垒。 可以使用原子层沉积技术，通过在沉积表面上吸附含有钽和硅的两种前体，然后在相同的操作中氧化两种前体来形成电介质层。