公开(公告)号：US09178011B2

公开(公告)日：2015-11-03

申请号：US14137003

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02 ,  H01L21/28 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract translation: 电介质层可以实现类似于具有设置在两个电介质层之间的导电层的基极电介质层的结晶取向。 通过提供具有与基底电介质层相似的晶体结构和晶格参数的导电层，晶体取向可以从基极介电层承载在导电层上，以影响电介质层。 该方法可以用于形成各向异性介电材料的电容器结构，沿着高介电常数的方向。

公开(公告)号：US20150187982A1

公开(公告)日：2015-07-02

申请号：US14141408

申请日：2013-12-26

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Amir Bayati ,  Dipankar Pramanik ,  Zhi-Wen Sun

IPC: H01L31/18

CPC classification number: H01L31/1832 ,  C23C14/0629 ,  C23C16/305 ,  H01L21/02411 ,  H01L21/02422 ,  H01L21/0248 ,  H01L21/02485 ,  H01L21/02499 ,  H01L21/02505 ,  H01L21/02562 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02631 ,  H01L31/02966 ,  H01L31/0749 ,  H01L31/18 ,  H01L31/1836 ,  Y02E10/541 ,  Y02P70/521

Abstract: Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blende crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Abstract translation: 本文提供的实施方案描述了形成碲化锰 - 碲化物（CMT）的方法，例如用于光伏器件中的方法。 提供了包括具有闪锌矿晶体结构的材料的基板。 CMT形成在衬底之上。 在CMT的形成过程中，维持富阳离子处理条件。 当与常规形成的CMT相比时，所得到的CMT可以更容易地被提供有p型掺杂剂。

公开(公告)号：US08907313B2

公开(公告)日：2014-12-09

申请号：US13719051

申请日：2012-12-18

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20140264507A1

公开(公告)日：2014-09-18

申请号：US14137866

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L27/146

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: CMOS imaging sensors having fluorine-passivated structures to reduce dark current are disclosed together with methods of making thereof. The CIS comprises an array of pixels on a substrate, each pixel comprising a pinned photodiode, an isolation trench adjacent to the pinned photodiode, and a plurality of transistors. Methods of preparing a CIS comprise providing a source of fluorine (F) atoms, and annealing in the presence of the source of F atoms. After the annealing, at least one silicon-containing surface or region in the CIS comprises Si—F bonds and is fluorine passivated.

Abstract translation: 公开了具有氟钝化结构以减少暗电流的CMOS成像传感器及其制造方法。 CIS包括衬底上的像素阵列，每个像素包括钉扎光电二极管，与被钉扎光电二极管相邻的隔离沟槽以及多个晶体管。 制备CIS的方法包括提供氟（F）原子源，并在F原子源存在下进行退火。 在退火之后，CIS中的至少一个含硅表面或区域包含Si-F键并被氟钝化。

公开(公告)号：US20140185357A1

公开(公告)日：2014-07-03

申请号：US13728739

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/147 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1633

Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Abstract translation: 适用于存储器件应用的转向元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，操纵元件可以包括第一电极，第二电极和夹在两个电极之间的渐变电介质层。 渐变电介质层可以包括从第一电极到第二电极的不同组成。 带隙的顶部和/或底部的分级能级可以是梯度介电层组成的结果，和/或电极的功函数可以被配置为抑制断开的隧道和热离子电流 和/或最大化导通状态和转向元件断开状态下的隧道和热离子电流的比例。

公开(公告)号：US20140175604A1

公开(公告)日：2014-06-26

申请号：US13725701

申请日：2012-12-21

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

IPC: H01L49/02

CPC classification number: H01L28/55 ,  C23C14/083 ,  C23C14/5806 ,  H01L21/28088 ,  H01L21/32051 ,  H01L28/40 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/785

Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.

Abstract translation: 含有二氧化钼（MoO2）的电极可用于电子元件，如存储器或逻辑器件。 含有二氧化钼的电极也可以具有很少的或没有钼元素，以及一部分氧化钼，例如Mo 2 x，x在2和3之间。氧化钼可以以三氧化钼MoO 3或Magneli相存在，例如 如Mo4O11，MO8O23或Mo9O26。 含二氧化钼的电极可以通过将包含钼层和氧化钼层的多层退火而形成。 多层的氧含量可以被配置为完全或基本完全地与钼反应形成二氧化钼，同时留下少量过量的x> 2的氧化钼MoO x。

公开(公告)号：US20160181091A1

公开(公告)日：2016-06-23

申请号：US14576853

申请日：2014-12-19

Applicant: Intermolecular, Inc.

Inventor： Sandip Niyogi ,  Sergey Barabash ,  Federico Nardi ,  Dipankar Pramanik

IPC: H01L21/02

CPC classification number: H01L29/516

Abstract: Embodiments provided herein describe systems and methods for forming ferroelectric materials. A trench body may be provided. A trench may be formed in the trench body. A dielectric material and a filler material may be deposited within the trench. The filler material may be heated such that a stress is exerted on the dielectric material before the dielectric material is heated to generate a ferroelectric phase within the dielectric material. A non-contiguous layer may be formed above a substrate. A second layer including a high-k dielectric material may be formed above the first layer. The high-k dielectric material may be heated to generate a ferroelectric phase within the high-k dielectric material.

Abstract translation: 本文提供的实施例描述了用于形成铁电材料的系统和方法。 可以提供沟槽体。 可以在沟槽体中形成沟槽。 介电材料和填充材料可以沉积在沟槽内。 填充材料可以被加热，使得在介电材料被加热之前在电介质材料上施加应力以在电介质材料内产生铁电相。 可以在衬底之上形成不连续的层。 可以在第一层之上形成包括高k电介质材料的第二层。 可以加热高k介电材料以在高k电介质材料内产生铁电相。

公开(公告)号：US09224799B2

公开(公告)日：2015-12-29

申请号：US14145117

申请日：2013-12-31

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L49/02 ,  H01L27/08 ,  H01L29/66 ,  H01L29/94 ,  H01L27/108

CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L29/66181 ,  H01L29/94

Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

Abstract translation: 提供用于集成电路的电容器堆叠以及制造这些堆叠的方法。 电容器堆叠包括电介质层和一个或两个内部电极层，例如正的内部电极层和负的内部电极层。 内部电极层直接与介电层接触。 堆叠还可以包括外部电极层。 内部电极层是化学稳定的或弱的化学不稳定的，同时基于相应的相图与介电层接触。 此外，正内电极层的电子亲和力可能小于电介质层的电子亲和力。 负的内电极层的电子亲和力和带隙的总和可以小于电介质层的电子亲和力。 在一些实施例中，内部电极层由重掺杂的半导体材料形成，例如砷化镓或砷化镓铝。

公开(公告)号：US09222170B2

公开(公告)日：2015-12-29

申请号：US13721606

申请日：2012-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L21/02 ,  H01L23/58 ,  C23C16/40 ,  H01L45/00 ,  H01L27/12 ,  H01L27/24 ,  C23C16/02 ,  C30B25/04 ,  C30B29/16 ,  C30B29/60 ,  H01L29/66 ,  H01L29/78 ,  B82Y40/00 ,  H01L27/06 ,  H01L49/02

CPC classification number: C23C16/405 ,  B82Y40/00 ,  C23C16/0272 ,  C30B25/04 ,  C30B29/16 ,  C30B29/60 ,  H01L21/02186 ,  H01L27/0629 ,  H01L27/1233 ,  H01L27/2436 ,  H01L28/40 ,  H01L29/66795 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L2924/0002 ,  Y10S977/811 ,  Y10S977/89 ,  Y10S977/932 ,  H01L2924/00

Abstract: Anisotropic materials, such as rutile TiO2, can exhibit dielectric constant of 170 along the tetragonal axis of (001) direction, and dielectric constant of 86 along directions perpendicular to the tetragonal axis. Layer of anisotropic material nanorods, such as TiO2 nanorods, can form a seed layer to grow a dielectric layer that can exhibit the higher dielectric constant value in a direction parallel to the substrate surface. The anisotropic layer can then be patterned to expose a surface normal to the high dielectric constant direction. A conductive material can be formed in contact with the exposed surface to create an electrode/dielectric stack along the direction of high dielectric constant.

Abstract translation: 各向异性材料，如金红石TiO2，沿（001）方向的四方轴表现介电常数为170，介电常数为86，沿垂直于四方轴的方向。 诸如TiO 2纳米棒的各向异性材料纳米棒的层可以形成种子层以生长在平行于衬底表面的方向上可以表现出更高的介电常数值的电介质层。 然后可以将各向异性层图案化以暴露垂直于高介电常数方向的表面。 可以形成与暴露表面接触的导电材料，以沿着高介电常数的方向产生电极/电介质堆叠。

公开(公告)号：US09105704B2

公开(公告)日：2015-08-11

申请号：US13722931

申请日：2012-12-20

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: H01L21/3065 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。