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    PIEZOELECTRONIC DEVICE WITH NOVEL FORCE AMPLIFICATION
    32.
    发明申请
    PIEZOELECTRONIC DEVICE WITH NOVEL FORCE AMPLIFICATION 有权
    具有新力放大的PIEZOELECTRONIC DEVICE

    公开(公告)号：US20150255699A1

    公开(公告)日：2015-09-10

    申请号：US14577279

    申请日：2014-12-19

    申请人： International Business Machines Corporation

    发明人： Bruce G. Elmegreen ,  Marcelo A. Kuroda ,  Xiao Hu Liu ,  Glenn J. Martyna ,  Dennis M. Newns ,  Paul M. Solomon

    IPC分类号： H01L41/047 ,  H01L41/09

    CPC分类号： H01L49/00 ,  H01L41/0986

    摘要： A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

    摘要翻译： 具有新颖的力放大的压电装置包括第一电极; 设置在所述第一电极上的压电层; 设置在压电层上的第二电极; 设置在所述第二电极上的绝缘体; 设置在绝缘体上的压阻层; 设置在所述绝缘体上的第三电极; 设置在所述绝缘体上的第四电极; 围绕层和电极的半刚性外壳; 其中半刚性壳体与第一，第三和第四电极和压阻层接触; 其中所述半刚性壳体包括空隙。 第三和第四电极在同一平面上并且在横向上彼此分开一段距离。

    Piezoelectronic memory
    33.
    发明授权
    Piezoelectronic memory 有权
    压电记忆

    公开(公告)号：US09058868B2

    公开(公告)日：2015-06-16

    申请号：US13719965

    申请日：2012-12-19

    申请人： International Business Machines Corporation

    发明人： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns ,  Paul M. Solomon

    IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/22 ,  H01L49/00

    CPC分类号： G11C13/0002 ,  G11C11/22 ,  H01L49/00

    摘要： A memory element includes a first piezotronic transistor coupled to a second piezotronic transistor; the first and second piezotronic transistors each comprising a piezoelectric (PE) material and a piezoresistive (PR) material, wherein an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.

    摘要翻译： 存储元件包括耦合到第二压电电子晶体管的第一压电电子晶体管; 第一和第二压电电子晶体管，每个包括压电（PE）材料和压阻（PR）材料，其中PR材料的电阻取决于通过施加的压力施加到PR材料上的施加的PE材料上的电压 由PE材料。

    PIEZOELECTRONIC MEMORY
    35.
    发明申请
    PIEZOELECTRONIC MEMORY 有权
    PIEZOELECTRONIC存储器

    公开(公告)号：US20140169078A1

    公开(公告)日：2014-06-19

    申请号：US13719965

    申请日：2012-12-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns ,  Paul M. Solomon

    IPC分类号： G11C11/40 ,  H01L29/84

    CPC分类号： G11C13/0002 ,  G11C11/22 ,  H01L49/00

    摘要： A memory element includes a first piezotronic transistor coupled to a second piezotronic transistor; the first and second piezotronic transistors each comprising a piezoelectric (PE) material and a piezoresistive (PR) material, wherein an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.

    摘要翻译： 存储元件包括耦合到第二压电电子晶体管的第一压电电子晶体管; 第一和第二压电电子晶体管，每个包括压电（PE）材料和压阻（PR）材料，其中PR材料的电阻取决于通过施加的压力施加到PR材料上的施加的PE材料上的电压 由PE材料。

    Piezoelectronic device with novel force amplification
    36.
    发明授权
    Piezoelectronic device with novel force amplification 有权

    公开(公告)号：US10964881B2

    公开(公告)日：2021-03-30

    申请号：US15825171

    申请日：2017-11-29

    申请人： International Business Machines Corporation

    发明人： Bruce G. Elmegreen ,  Marcelo A. Kuroda ,  Xiao Hu Liu ,  Glenn J. Martyna ,  Dennis M. Newns ,  Paul M. Solomon

    IPC分类号： H01L41/09

    摘要： A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

    Piezoelectronic switch device for RF applications
    38.
    发明授权
    Piezoelectronic switch device for RF applications 有权

    公开(公告)号：US09881759B2

    公开(公告)日：2018-01-30

    申请号：US14745521

    申请日：2015-06-22

    申请人： International Business Machines Corporation

    发明人： Matthew W. Copel ,  Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns ,  Thomas M. Shaw ,  Paul M. Solomon

    IPC分类号： H01L41/08 ,  H01L25/00 ,  H01H57/00 ,  H01H49/00

    CPC分类号： H01H57/00 ,  H01H49/00 ,  H01H2057/006

    摘要： A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

    Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers
    39.
    发明授权
    Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers 有权
    低压晶体管和具有多个堆叠压电层的逻辑器件

    公开(公告)号：US09590167B2

    公开(公告)日：2017-03-07

    申请号：US15248488

    申请日：2016-08-26

    申请人： International Business Machines Corporation

    发明人： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

    IPC分类号： H01L41/107 ,  H01L41/083 ,  H01L41/047 ,  H01L41/187

    CPC分类号： H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

    摘要： A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

    摘要翻译： 压电电子晶体管器件包括以堆叠配置布置的第一压电（PE）层，第二PE层和压阻（PR）层，其中PR层的电阻取决于施加的电压跨越第一和第二 PE层通过施加的压力由第一和第二PE层施加到PR层。 压电电子逻辑器件包括第一和第二压电晶体管（PET），其中第一PET的第一和第二PE层具有比第二PET的横截面积小的横截面面积，使得跨越第二PET层的PE层的电压降 第一PET在第一PET的PR层中产生小于由第二PET的PE层上的相同电压降产生的第二PET的PR层中的第二压力的第一压力。

    LOW VOLTAGE TRANSISTOR AND LOGIC DEVICES WITH MULTIPLE, STACKED PIEZOELECTRONIC LAYERS
    40.
    发明申请
    LOW VOLTAGE TRANSISTOR AND LOGIC DEVICES WITH MULTIPLE, STACKED PIEZOELECTRONIC LAYERS 有权
    低电压晶体管和具有多个堆叠的电子层的逻辑器件

    公开(公告)号：US20160359099A1

    公开(公告)日：2016-12-08

    申请号：US15248488

    申请日：2016-08-26

    申请人： International Business Machines Corporation

    发明人： Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns

    IPC分类号： H01L41/107 ,  H01L41/047 ,  H01L41/187 ,  H01L41/083

    CPC分类号： H01L41/107 ,  H01L41/047 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/183 ,  H01L41/1876 ,  H01L49/00

    摘要： A piezoelectronic transistor device includes a first piezoelectric (PE) layer, a second PE layer, and a piezoresistive (PR) layer arranged in a stacked configuration, wherein an electrical resistance of the PR layer is dependent upon an applied voltage across the first and second PE layers by an applied pressure to the PR layer by the first and second PE layers. A piezoelectronic logic device includes a first and second piezoelectric transistor (PET), wherein the first and second PE layers of the first PET have a smaller cross sectional area than those of the second PET, such that a voltage drop across the PE layers of the first PET creates a first pressure in the PR layer of the first PET that is smaller than a second pressure in the PR layer of the second PET created by the same voltage drop across the PE layers of the second PET.

    摘要翻译： 压电电子晶体管器件包括以堆叠配置布置的第一压电（PE）层，第二PE层和压阻（PR）层，其中PR层的电阻取决于施加的电压跨越第一和第二 PE层通过施加的压力由第一和第二PE层施加到PR层。 压电电子逻辑器件包括第一和第二压电晶体管（PET），其中第一PET的第一和第二PE层具有比第二PET的横截面积小的横截面面积，使得跨越第二PET层的PE层的电压降 第一PET在第一PET的PR层中产生小于由第二PET的PE层上的相同电压降产生的第二PET的PR层中的第二压力的第一压力。