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31.发明申请Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效在单元中并联连接沟槽电容器的多端口存储器制造方法公开(公告)号：US20090176339A1
公开(公告)日：2009-07-09
申请号：US12316748
申请日：2008-12-16
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。
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公开(公告)号：US06833305B2
公开(公告)日：2004-12-21
申请号：US10838018
申请日：2004-05-03
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
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33.发明授权Structure and process for compact cell area in a stacked capacitor cell array 失效叠层电容器阵列中紧凑单元面积的结构和工艺公开(公告)号：US06455886B1
公开(公告)日：2002-09-24
申请号：US09636564
申请日：2000-08-10
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L29/66181
摘要： A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.
摘要翻译： 一种用于形成的方法，以及具有连接到层叠电容器单元的垂直取向的晶体管的半导体器件的结构，其中电容器的接触面积使得能够实现紧凑的电池。 垂直取向的晶体管形成在掩埋位线上方的衬底的槽中。 栅极导体可以形成在掩埋位线上方的槽中，源极和漏极扩散沿着槽的侧壁间隔开。 在半导体衬底中形成隔离区以隔离晶体管。 在与掩埋位线的方向垂直的方向上在半导体衬底的表面上形成字线。 在相邻字线之间的有源区域的接触区域处，在半导体衬底的表面上方形成电容器触点。 有源区域是菱形形状，能够实现低电容器接触电阻，小位线和字线间距，从而实现紧凑的电容器单元。
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公开(公告)号：US06440872B1
公开(公告)日：2002-08-27
申请号：US09706468
申请日：2000-11-03
IPC分类号： H01L2100
CPC分类号： H01L27/10867 , H01L27/10876
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.
摘要翻译： 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。
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公开(公告)号：US06420749B1
公开(公告)日：2002-07-16
申请号：US09602427
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
发明人： Ramachandra Divakaruni , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/76232 , H01L21/76895 , H01L21/823475 , H01L27/10897
摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.
摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。
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公开(公告)号：US06414347B1
公开(公告)日：2002-07-02
申请号：US09790011
申请日：2001-02-09
IPC分类号： H01L2972
CPC分类号： H01L27/10864 , H01L21/2255 , H01L21/26586 , H01L27/10841 , H01L29/66666 , H01L29/7827
摘要： An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.
摘要翻译： 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。
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37.发明授权Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact 失效用于提供具有无边界扩散接触的低GIDL双功函数栅极掺杂的方法和装置公开(公告)号：US06333220B1
公开(公告)日：2001-12-25
申请号：US09325943
申请日：1999-06-04
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823468 , H01L27/10873
摘要： A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.
摘要翻译： 提供半导体结构以及相应的制造这种结构的方法。 该方法和结构可以包括提供半导体衬底，半导体衬底上的栅极绝缘体，在栅极绝缘体上包括本征多晶硅的导体，多晶硅上的硅化物层和在硅化物层上的绝缘帽。 可以沿着硅化物层和绝缘盖的侧面设置绝缘间隔物。 多晶硅可以掺杂有第一导电型掺杂剂。 第一导电型掺杂剂可以扩散在多晶硅上以形成掺杂的多晶硅层。 栅极侧壁层可以形成在掺杂多晶硅层的侧面上。 门侧壁层的鸟嘴也可以形成在多晶硅的角部。
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公开(公告)号：US06274441B1
公开(公告)日：2001-08-14
申请号：US09560073
申请日：2000-04-27
IPC分类号： H01L2170
CPC分类号： H01L29/1045 , H01L21/266 , H01L27/10861 , H01L27/10873 , H01L27/10888 , H01L29/1083 , H01L29/6653 , H01L29/66659
摘要： A method for fabricating a MOSFET device including a halo implant comprising providing a semiconductor substrate, a gate insulator layer, a conductor layer, an overlying silicide layer, and an insulating cap; patterning and etching the silicide layer and the insulating cap; providing insulating spacers along sides of said silicide layer and insulating cap; implanting node and bitline N+ diffusion regions; patterning a photoresist layer to protect the node diffusion region and supporting PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; etching exposed spacer material from the side of said silicide layer and insulating cap; implanting a P-type impurity halo implant into the exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulating spacer along the exposed side of said silicide layer and insulating cap.
摘要翻译： 一种制造包括卤素注入的MOSFET器件的方法，包括提供半导体衬底，栅极绝缘体层，导体层，上覆硅化物层和绝缘帽; 图案化和蚀刻硅化物层和绝缘帽; 在所述硅化物层和绝缘盖的侧面提供绝缘垫片; 植入节点和位线N +扩散区域; 图案化光致抗蚀剂层以保护节点扩散区域并支持PFET源极和漏极区域并暴露位线扩散区域和NFET源极和漏极区域; 从所述硅化物层和绝缘盖的侧面蚀刻暴露的间隔物材料; 将P型杂质卤素注入植入暴露的位线扩散区并支持NFET源极和漏极区; 并剥离光致抗蚀剂层，并沿着所述硅化物层和绝缘帽的暴露侧提供绝缘间隔物。
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39.发明授权Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 有权在EDRAM阵列中形成双功能高性能支持MOSFET的方法公开(公告)号：US06261894B1
公开(公告)日：2001-07-17
申请号：US09706492
申请日：2000-11-03
IPC分类号： H01L218234
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译： 提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。 这里描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连， 加工成本。 还提供了双功能功能的高性能支持具有栅极导体保护环和/或局部互连的MOSFET / EDRAM阵列。
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公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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