公开(公告)号：US06707728B2

公开(公告)日：2004-03-16

申请号：US10152267

申请日：2002-05-21

Applicant: Jae Jin Lee

Inventor： Jae Jin Lee

IPC: G11C700

CPC classification number: G11C7/106 ,  G11C5/14 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/22

Abstract: A signal delay control circuit for use in a semiconductor memory device is disclosed. The circuit includes a first reference voltage generating unit for generating a first reference voltage; a second reference voltage generating unit for generating a second reference voltage that is lower than the first reference voltage; a control signal generating unit for generating a clock signal to drive input and output operations of internal circuits; and an impedance circuit in circuit with the first and second reference voltage generating units for generating a plurality of reference voltages to be applied to the internal circuits wherein the reference voltages are set in accordance with a distance between the control signal generating unit and the respective one of the internal circuits.

公开(公告)号：US06539216B1

公开(公告)日：2003-03-25

申请号：US09475053

申请日：1999-12-30

Applicant: Eung Gie Oh ,  Min Gun Kim ,  Sung Weon Kang ,  Jae Jin Lee

Inventor： Eung Gie Oh ,  Min Gun Kim ,  Sung Weon Kang ,  Jae Jin Lee

IPC: H04B126

CPC classification number: H04B1/18

Abstract: A microwave frequency converting receiver of an RF unit should be generally used in wireless/mobile communications systems such as cellular, PCS, WLL and IMT2000 systems and also have low power consumption, low-noise characteristic, high gain and small size. In order to produce the above frequency converting receiver, a multi-band and multi-mode frequency converting receiver for use in a wireless mobile communications system comprises a wideband low-noise amplifier for amplifying a radio frequency input signal, a frequency mixer for generating an intermediate frequency signal having a relatively high linearity by mixing a local oscillator frequency signal and the amplified radio frequency signal outputted from the wideband low noise amplifier, an intermediate frequency amplifier for producing a final intermediate frequency signal by amplifying the intermediate frequency signal derived from the frequency mixer and an input matching circuit for receiving a microwave signal within a frequency band of the wireless mobile communications system, impedance-matching the received microwave signal to the radio frequency input signal of the wideband low-noise amplifier and determining an operating frequency band of the frequency converting receiver.

Abstract translation: RF单元的微波频率转换接收机通常应用在诸如蜂窝，PCS，WLL和IMT2000系统的无线/移动通信系统中，并且还具有低功耗，低噪声特性，高增益和小尺寸。 为了生产上述频率转换接收机，用于无线移动通信系统的多频和多模式频率转换接收机包括用于放大射频输入信号的宽带低噪声放大器，用于产生 通过混合本地振荡器频率信号和从宽带低噪声放大器输出的放大射频信号具有较高线性度的中频信号，用于通过放大从频率导出的中频信号来产生最终中频信号的中频放大器 混频器和用于在无线移动通信系统的频带内接收微波信号的输入匹配电路，将接收到的微波信号与宽带低噪声放大器的射频输入信号进行阻抗匹配，并确定该宽带低噪声放大器的工作频带 变频接收机。

公开(公告)号：US06448633B1

公开(公告)日：2002-09-10

申请号：US09444035

申请日：1999-11-19

Applicant: Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

Inventor： Jae Hak Yee ,  Young Suk Chung ,  Jae Jin Lee ,  Terry Davis ,  Chung Suk Han ,  Jae Hun Ku ,  Jae Sung Kwak ,  Sang Hyun Ryu

IPC: H01L23495

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed. The lead frame includes a paddle, a plurality of tie bars for supporting the comers of the paddle, a plurality of leads arranged at each of four sides or two facing sides of the paddle in such a fashion that they are spaced apart from an adjacent side of the paddle while extending perpendicularly to the associated side of the paddle, each of the leads having lead separation preventing means adapted to increase a bonding force of the lead to a resin encapsulate subsequently molded to encapsulate the lead frame for fabrication of the semiconductor package, and dam bars for supporting the leads and the tie bars. Additional package embodiments include exposed protrusions extending downward from the leads. The exposed protrusions are irradiated with a laser to remove set resin prior to a solder ball attachment step.

Abstract translation: 公开了一种用于制造半导体封装的引线框架。 引线框架的引线包括提供在每个内引线的自由端处的引线锁，其适于增加内引线与树脂封装件的结合力，从而有效地防止内引线的分离在所涉及的单个加工过程中发生 制造半导体封装。 还公开了使用引线框制造的半导体封装和用于半导体封装的制造方法。 引线框架包括桨，用于支撑桨的角的多个连杆，多个引线布置在桨的四个侧面或两个相对的侧面中，使得它们与相邻侧面间隔开 的叶片，同时垂直于桨叶的相关侧延伸，每个引线具有引线分离防止装置，其适于增加引线与随后模制的树脂封装件的结合力，以封装引线框架以制造半导体封装， 和用于支撑引线和连接条的阻挡条。 另外的封装实施例包括从引线向下延伸的暴露突起。 在焊球附着步骤之前，用激光照射暴露的突起以去除固化树脂。

公开(公告)号：US20140110745A1

公开(公告)日：2014-04-24

申请号：US14124974

申请日：2012-02-02

Applicant: Jae Jin Lee ,  Sung Ho Choi ,  Duk In Kang

Inventor： Jae Jin Lee ,  Sung Ho Choi ,  Duk In Kang

IPC: H01L33/62

CPC classification number: H01L33/62 ,  H01L27/32 ,  H01L33/642 ,  H01L33/647 ,  H01L51/50 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: An LED package includes a lead frame, a housing part, and a lead heat dissipating part. The lead frame includes a first lead mounting an LED chip and a second lead spaced apart from the first lead. The housing part covers a portion of the lead frame and includes an opening part for exposing the LED chip, a first side corresponding to a support side contacting the first lead and the second lead, and a second side opposite to the first side. The lead heat dissipating part is extended from the first lead and exposed partially to the first side of the housing part. Herein, the first side of the housing part is thicker than the second side.

Abstract translation: LED封装包括引线框架，壳体部分和引线散热部件。 引线框架包括安装LED芯片的第一引线和与第一引线间隔开的第二引线。 壳体部分覆盖引线框架的一部分并且包括用于暴露LED芯片的开口部分，对应于接触第一引线和第二引线的支撑侧的第一侧和与第一侧相对的第二侧。 引线散热部分从第一引线延伸并部分暴露于壳体部分的第一侧。 这里，壳体部分的第一侧比第二侧厚。

公开(公告)号：US08559524B2

公开(公告)日：2013-10-15

申请号：US12837022

申请日：2010-07-15

Applicant: Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jae Jin Lee ,  Moo Kyoung Chung ,  Kyung Su Kim ,  Jun Young Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/26

CPC classification number: H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.

Abstract translation: 公开了一种基于数据和功能分解方案的视频解码装置和方法。 基于数据和功能分割方案的视频解码装置包括：可变长度解码单元，对比特流执行可变长度解码和解析以获取残差数据和解码参数，并且逐行分割残留数据和解码参数; 并且N（N是2或更大的自然数）将数量分解解量化和逆离散余弦变换（IDCT），运动矢量预测，帧内预测和运动补偿，视频恢复和去块功能的簇数分为M个函数，获取 按照列逐列的残差数据，解码参数和宏块（MB）处理信息，并将通过列获取的信息拆分为M个函数以进行处理。

公开(公告)号：US08519734B2

公开(公告)日：2013-08-27

申请号：US13162676

申请日：2011-06-17

Applicant: Chun Seok Jeong ,  Jae Jin Lee

Inventor： Chun Seok Jeong ,  Jae Jin Lee

IPC: H03K19/003

CPC classification number: G11C7/20 ,  G11C29/883 ,  G11C2029/4402 ,  H01L2224/16

Abstract: A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.

Abstract translation: 具有第一和第二芯片的半导体装置包括设置在第一芯片中的第一操作单元，并且被配置为根据第一修复信号对初始码执行预定的算术运算，并生成第一操作码; 以及第二操作单元，设置在所述第二芯片中，并且被配置为根据第二修复信号对所述第一操作码执行所述预定算术运算，并生成第二操作码。

公开(公告)号：US08358555B2

公开(公告)日：2013-01-22

申请号：US12835978

申请日：2010-07-14

Applicant: Jin Youp Cha ,  Jae Jin Lee

Inventor： Jin Youp Cha ,  Jae Jin Lee

IPC: G11C17/18 ,  G11C17/00 ,  H01H85/00

CPC classification number: G11C17/16 ,  G11C29/785

Abstract: A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

Abstract translation: 熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。

公开(公告)号：US08035146B2

公开(公告)日：2011-10-11

申请号：US12820092

申请日：2010-06-21

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: H01L27/115

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.

Abstract translation: 非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。 根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

公开(公告)号：US20110187429A1

公开(公告)日：2011-08-04

申请号：US12838332

申请日：2010-07-16

Applicant: Sang Jin BYEON ,  Jae Jin Lee

Inventor： Sang Jin BYEON ,  Jae Jin Lee

IPC: H03L7/00

CPC classification number: H03L7/00

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US07741668B2

公开(公告)日：2010-06-22

申请号：US11717081

申请日：2007-03-13

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: H01L29/94

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

Abstract: A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

Abstract translation: 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，并且在绝缘层上形成包括N型漏极区，P型沟道区和N型源极区的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。