公开(公告)号：US20060093924A1

公开(公告)日：2006-05-04

申请号：US10904308

申请日：2004-11-03

申请人： James Adkisson ,  Eric Coker ,  Christopher Magg ,  Jed Rankin ,  Anthony Stamper

发明人： James Adkisson ,  Eric Coker ,  Christopher Magg ,  Jed Rankin ,  Anthony Stamper

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/72 ,  G03F1/70

摘要： A method for correction of defects in lithography masks includes determining the existence of mask defects on an original mask, and identifying a stitchable zone around each of the mask defects found on the original mask. Each of the identified stitchable zones on the original mask is blocked out such that circuitry within the stitchable zones is not printed out during exposure of the original mask. A repair mask is formed, the repair mask including corrected circuit patterns from each of the identified stitchable zones.

摘要翻译： 用于校正光刻掩模中的缺陷的方法包括确定原始掩模上的掩模缺陷的存在，以及识别在原始掩模上发现的每个掩模缺陷周围的可缝合区域。 原始掩模上的每个识别的可缝合区域被阻挡，使得在原始掩模曝光期间不能打印出可缝合区域内的电路。 形成修复掩模，修复掩模包括来自每个识别的可缝合区域的校正电路图案。

公开(公告)号：US20060091442A1

公开(公告)日：2006-05-04

申请号：US11298800

申请日：2005-12-09

申请人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

发明人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L29/94

CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

公开(公告)号：US20070026617A1

公开(公告)日：2007-02-01

申请号：US11495518

申请日：2006-07-31

申请人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

发明人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L21/20 ,  H01L21/44

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US20050030149A1

公开(公告)日：2005-02-10

申请号：US10604609

申请日：2003-08-04

申请人： James Adkisson ,  Anthony Stamper

发明人： James Adkisson ,  Anthony Stamper

IPC分类号： H01C10/00 ,  H01L27/08 ,  H01C7/10

CPC分类号： H01C10/00 ,  H01L27/0802

摘要： The present invention discloses a device having a resistor; a heater disposed proximate to the resistor and capable of raising the temperature of the resistor; a dielectric disposed between the heater and the resistor; and a tuner electrically coupled to the resistor, wherein the heater adjusts the resistance of the resistor in response to the tuner.

摘要翻译： 本发明公开了一种具有电阻器的器件; 靠近电阻器设置并能够提高电阻器的温度的加热器; 设置在加热器和电阻器之间的电介质; 以及电耦合到所述电阻器的调谐器，其中所述加热器响应于所述调谐器调节所述电阻器的电阻。

公开(公告)号：US20050001216A1

公开(公告)日：2005-01-06

申请号：US10867772

申请日：2004-06-16

申请人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

发明人： James Adkisson ,  Paul Agnello ,  Arne Ballantine ,  Rama Divakaruni ,  Erin Jones ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US20080017857A1

公开(公告)日：2008-01-24

申请号：US11859890

申请日：2007-09-24

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Matthew Grady ,  Thomas Sopchak ,  David Vallett

IPC分类号： H01L23/58

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US20070164337A1

公开(公告)日：2007-07-19

申请号：US11687000

申请日：2007-03-16

申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

摘要翻译： 提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。 本发明的方法包括分别形成CMOS结构和铁电输送晶片。 然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。 然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。 电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

公开(公告)号：US20070023796A1

公开(公告)日：2007-02-01

申请号：US11161224

申请日：2005-07-27

申请人： James Adkisson ,  John Ellis-Monaghan

发明人： James Adkisson ,  John Ellis-Monaghan

IPC分类号： H01L31/113 ,  H01L31/062

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/1463

摘要： A novel pixel sensor cell structure and method of manufacture. The pixel sensor cell includes a collection well region of a first conductivity type and a pinning layer formed in a substrate. The pinning layer includes a first impurity region of a second conductivity type and a second impurity region of the second conductivity type. The first and second impurity regions can be independently formed to affect multiple parameters of the pixel sensor cell.

摘要翻译： 一种新颖的像素传感器单元结构及其制造方法。 像素传感器单元包括第一导电类型的收集阱区域和形成在衬底中的钉扎层。 钉扎层包括第二导电类型的第一杂质区和第二导电类型的第二杂质区。 可以独立地形成第一和第二杂质区域以影响像素传感器单元的多个参数。

公开(公告)号：US20060073689A1

公开(公告)日：2006-04-06

申请号：US10711771

申请日：2004-10-04

申请人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

发明人： James Adkisson ,  John Ellis-Monaghan ,  Glenn MacDougall ,  Dale Martin ,  Kirk Peterson ,  Bruce Porth

IPC分类号： H01L21/3205

CPC分类号： H01L21/265 ,  H01L21/28035 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

摘要翻译： 一种制造多晶硅线路和多晶硅栅极的方法，所述方法包括：提供衬底; 在所述基板的顶表面上形成介电层; 在所述电介质层的顶表面上形成多晶硅层; 用N掺杂物种注入多晶硅层，所述N掺杂物物质包含在所述多晶硅层内; 用含氮物质注入多晶硅层，含氮物质基本上包含在多晶硅层内。

公开(公告)号：US20060036975A1

公开(公告)日：2006-02-16

申请号：US10710879

申请日：2004-08-10

申请人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Francis Gravel ,  Leendert Huisman ,  Phillip Nigh ,  Leah Pastel ,  Kenneth Rowe ,  Thomas Sopchak ,  David Sweenor

发明人： James Adkisson ,  Greg Bazan ,  John Cohn ,  Francis Gravel ,  Leendert Huisman ,  Phillip Nigh ,  Leah Pastel ,  Kenneth Rowe ,  Thomas Sopchak ,  David Sweenor

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G01R31/318342

摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.

摘要翻译： 一种半导体芯片缺陷诊断方法。 该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。