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公开(公告)号：US20130154003A1
公开(公告)日：2013-06-20
申请号：US13329440
申请日：2011-12-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/66492 , H01L29/66583 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.
摘要翻译： 形成集成电路结构的方法将第一补偿植入物植入衬底。 该方法在衬底中的第一补偿植入物上形成掩模。 掩模包括暴露基板的通道位置的开口。 该方法将第二补偿植入物植入衬底的通道位置。 第二补偿植入物通过掩模中的开口并以与衬底的顶表面垂直的角度形成。 第二补偿植入件相对于沟道位置的相对的第二侧被定位成更靠近通道位置的第一侧，并且第二补偿植入物包括具有与半导体沟道植入物相同的掺杂极性的材料。 然后，该方法在掩模的开口中在衬底的通道位置之上形成栅极导体。
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公开(公告)号：US07416941B2
公开(公告)日：2008-08-26
申请号：US11426623
申请日：2006-06-27
IPC分类号： H01L21/8247
CPC分类号： H01L29/785 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7887 , Y10S438/954
摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.
摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。
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公开(公告)号：US07268397B2
公开(公告)日：2007-09-11
申请号：US11160360
申请日：2005-06-21
IPC分类号： H01L29/78
CPC分类号： H01L29/78606 , H01L27/0248 , H01L29/42384 , H01L29/785
摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.
摘要翻译： 翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。 鳍片有一个通道区域，以及源极和漏极区域。 栅极导体位于沟道区域的上方。 绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。 散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。
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公开(公告)号：US07091551B1
公开(公告)日：2006-08-15
申请号：US10907712
申请日：2005-04-13
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7887 , Y10S438/954
摘要： A four-bit FinFET memory cell, method of fabricating four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.
摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。
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公开(公告)号：US07387937B2
公开(公告)日：2008-06-17
申请号：US11756078
申请日：2007-05-31
IPC分类号： H01L21/336
CPC分类号： H01L29/78606 , H01L27/0248 , H01L29/42384 , H01L29/785
摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.
摘要翻译： 翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。 鳍片有一个通道区域，以及源极和漏极区域。 栅极导体位于沟道区域的上方。 绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。 散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。
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36.发明授权Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权具有拉伸和/或压缩应力的半导体器件和制造方法公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。
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公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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公开(公告)号：US20120168873A1
公开(公告)日：2012-07-05
申请号：US12984773
申请日：2011-01-05
IPC分类号： H01L21/70 , G06F17/50 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26586 , H01L21/823807 , H01L29/66659
摘要： Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.
摘要翻译： 传输门，制造传输门的方法和传输门的设计结构。 传输门包括n沟道场效应晶体管，其特征在于不对称掺杂的端子和由不对称掺杂的端子表征的p沟道场效应晶体管。
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公开(公告)号：US20110193163A1
公开(公告)日：2011-08-11
申请号：US12702684
申请日：2010-02-09
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
摘要翻译： 场效应器件包括设置在绝缘体上硅（SOI）层上的沟道区域，设置在沟道区上的栅极部分，设置在SOI层上的源极区域，并连接到具有水平表面和垂直表面的沟道区域 垂直于装置的线性轴排列的垂直表面，包括源区域的水平表面和垂直表面的硅化物部分，包括与源区域的水平表面和垂直表面接触的金属材料的触点， 以及连接到设置在SOI层上的沟道区的漏极区。
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公开(公告)号：US07829407B2
公开(公告)日：2010-11-09
申请号：US11561488
申请日：2006-11-20
IPC分类号： H01L21/336 , H01L21/84 , H01L29/78
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译： 一种包括半导体材料的半导体器件，该半导体材料具有形成在该弯曲处的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构。 一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力 栅结构的区域。
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