利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

292 条记录 (耗时 0.024 秒)

    Methods of fabricating nanostructures
    3.
    发明授权
    Methods of fabricating nanostructures 失效
    制造纳米结构的方法

    公开(公告)号：US07981772B2

    公开(公告)日：2011-07-19

    申请号：US12344696

    申请日：2008-12-29

    申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jeffrey W. Sleight

    发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Jeffrey W. Sleight

    IPC分类号： H01L21/3213

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  Y10S977/888

    摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.

    摘要翻译： 示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。 制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。 该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。 该方法还包括分离Si材料以形成硅纳米线。

    CURVED FINFETS
    4.
    发明申请
    CURVED FINFETS 有权
    弯曲的熔体

    公开(公告)号：US20080164535A1

    公开(公告)日：2008-07-10

    申请号：US11621228

    申请日：2007-01-09

    申请人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    发明人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7843

    摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.

    摘要翻译： 一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。 然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。 接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。 翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的 移动，中央部分不能自由移动。 在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。 因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

    Curved FINFETs
    5.
    发明授权
    Curved FINFETs 有权
    弯曲的FINFET

    公开(公告)号：US07538391B2

    公开(公告)日：2009-05-26

    申请号：US11621228

    申请日：2007-01-09

    申请人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    发明人： Dureseti Chidambarrao ,  Shreesh Narasimha ,  Edward J. Nowak ,  John J. Pekarik ,  Jeffrey W. Sleight ,  Richard Q. Williams

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7843

    摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.

    摘要翻译： 一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。 然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。 接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。 翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的 移动，中央部分不能自由移动。 在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。 因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS
    6.
    发明申请
    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS 失效
    不同厚度的氧化硅纳米线场效应晶体管

    公开(公告)号：US20110133280A1

    公开(公告)日：2011-06-09

    申请号：US12631148

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.

    摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。

    Different thickness oxide silicon nanowire field effect transistors
    7.
    发明授权
    Different thickness oxide silicon nanowire field effect transistors 失效
    不同厚度的氧化硅纳米线场效应晶体管

    公开(公告)号：US08008146B2

    公开(公告)日：2011-08-30

    申请号：US12631148

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.

    摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。

    Nanowire Stress Sensors and Stress Sensor Integrated Circuits, Design Structures for a Stress Sensor Integrated Circuit, and Related Methods
    8.
    发明申请
    Nanowire Stress Sensors and Stress Sensor Integrated Circuits, Design Structures for a Stress Sensor Integrated Circuit, and Related Methods 有权
    纳米线应力传感器和应力传感器集成电路，应力传感器集成电路的设计结构及相关方法

    公开(公告)号：US20110095267A1

    公开(公告)日：2011-04-28

    申请号：US12605523

    申请日：2009-10-26

    申请人： Andres Bryant ,  Oki Gunawan ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

    发明人： Andres Bryant ,  Oki Gunawan ,  Shih-Hsien Lo ,  Jeffrey W. Sleight

    IPC分类号： H01L29/06 ,  G06F17/50 ,  G01B7/16

    CPC分类号： H01L29/66477 ,  B82Y10/00 ,  B82Y40/00 ,  G01B7/16 ,  G01B7/18 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/724 ,  Y10S977/938 ,  Y10S977/956

    摘要： Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.

    摘要翻译： 使用一个或多个纳米线场效应晶体管作为应力敏感元件的应力传感器和应力传感器集成电路，以及体现在用于设计，制造或测试集成电路的机器可读介质中的应力传感器集成电路的设计结构，以及 相关方法。 应力传感器和应力传感器集成电路包括一对或多对栅极全环场效应晶体管，其包括一个或多个纳米线作为沟道区。 每个场效应晶体管的纳米线被配置为响应于从物体传递的机械应力而改变长度。 与场效应晶体管的电压输出差异表示转移的机械应力的大小。

    HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME
    9.
    发明申请
    HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME 审中-公开
    高密度指针式CMOS反相器，以及其制造和布局

    公开(公告)号：US20110291193A1

    公开(公告)日：2011-12-01

    申请号：US12788362

    申请日：2010-05-27

    申请人： Andres Bryant ,  Josephine B. Chang ,  Jeffrey W. Sleight

    发明人： Andres Bryant ,  Josephine B. Chang ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12 ,  H01L21/86

    CPC分类号： H01L27/1203 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

    摘要： A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.

    摘要翻译： 形成在SOI衬底上的高密度，不对称对接结CMOS反相器可以包括：非对称p-FET，其仅在p-FET的源极侧包括卤素注入; 一个不对称的n-FET，其仅在n-FET的源极侧包括一个卤素注入; 以及包括所述SOI衬底的区域的对接结，其中所述非对称n-FET的漏极区域和所述非对称p-FET的漏极区域直接物理接触。 可以通过以离子吸收结构覆盖CMOS反相器的第一FET的顺序过程形成非对称晕环植入物，并且仅向第二FET的源极侧施加成角度的离子辐射，去除离子吸收结构，覆盖第一 FET，具有第二离子吸收结构，并且仅向第二FET的源极侧施加成角度的离子辐射。 CMOS集成电路的布局显示可能需要高密度，不对称对接结CMOS反相器和其他CMOS电路的另一个接地规则的一个接地规则。