公开(公告)号：US08779475B2

公开(公告)日：2014-07-15

申请号：US13582432

申请日：2011-11-28

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L27/085 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/51 ,  H01L21/8258 ,  H01L29/20 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，形成在衬底上的绝缘隔离层，形成在绝缘隔离层中的第一有源区和第二有源区，其特征在于，第一有源区 区域层和/或第二有源区层比衬底高。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区，增加沟道区中的载流子迁移率，从而显着改善器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20130267073A1

公开(公告)日：2013-10-10

申请号：US13577252

申请日：2012-06-07

Applicant: Huaxiang Yin ,  Wei He ,  Huicai Zhong ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Wei He ,  Huicai Zhong ,  Chao Zhao ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L21/823431 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention discloses a method of manufacturing a fin field effect transistor, which comprises the steps of forming a plurality of first fin structures on a substrate, which extend along a first direction parallel to the substrate; forming a plurality of second fin structures on a substrate, which extend along a second direction parallel to the substrate and the second direction intersecting with the first direction; selectively removing a part of the second fin structures to form a plurality of gate lines; and selectively removing a part of the first fin structures to form a plurality of substrate lines. In the method of manufacturing a fin field effect transistor according to the present invention, the gate lines and substrate lines are formed simultaneously by first making uniform silicon wing lines and gate wing lines using a limiting photolithography patternizing technique and then performing a centralized cutting of the corresponding specific regions, thereby increasing uniformity and reducing process difficulty and cost.

Abstract translation: 本发明公开了一种制造鳍状场效应晶体管的方法，其特征在于包括以下步骤：沿着平行于衬底的第一方向延伸的衬底上形成多个第一鳍结构; 在基板上形成多个第二翅片结构，所述第二鳍结构沿着平行于所述基板的第二方向延伸并且所述第二方向与所述第一方向相交; 选择性地去除所述第二鳍结构的一部分以形成多个栅极线; 以及选择性地去除所述第一鳍结构的一部分以形成多条基片线。 在根据本发明的鳍状场效应晶体管的制造方法中，通过首先使用限制光刻图案化技术首先制造均匀的硅翼线和栅翼线，然后进行集中切割，同时形成栅极线和衬底线 相应的特定区域，从而增加均匀性，降低工艺难度和成本。

公开(公告)号：US08541296B2

公开(公告)日：2013-09-24

申请号：US13510730

申请日：2011-11-30

Applicant: Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

Inventor： Tao Yang ,  Chao Zhao ,  Jiang Yan ,  Junfeng Li ,  Yihong Lu ,  Dapeng Chen

IPC: H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/32139 ,  H01L29/51

Abstract: The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

Abstract translation: 本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。 根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。 它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

公开(公告)号：US08501500B2

公开(公告)日：2013-08-06

申请号：US13499288

申请日：2011-11-29

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li ,  Jiang Yan ,  Dapeng Chen

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L29/66545

Abstract: The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.

Abstract translation: 本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。 根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈， 准确地不会对晶片造成任何损坏。

公开(公告)号：US20130092986A1

公开(公告)日：2013-04-18

申请号：US13395608

申请日：2011-10-17

Applicant: Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

Inventor： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/82345 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.

Abstract translation: 一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。 栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。 因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

公开(公告)号：US20120261803A1

公开(公告)日：2012-10-18

申请号：US13394935

申请日：2011-10-17

Applicant: Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

Inventor： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC: H01L21/31 ,  H01L29/02

CPC classification number: C23C14/08 ,  C23C14/5806 ,  C23C16/401 ,  C23C16/56

Abstract: The present invention forms Hf1-xSixOy having a cubic phase or a tetragonal phase by doping a specific amount of SiO2 component into the high-K gate dielectric material HfO2 in combination with an optimized thermal processing technique, to thereby acquire a high-K gate dielectric thin film material having a greater bandgap, a higher K value and high thermal stability. Besides, the high-K gate dielectric thin film and a preparation method thereof proposed in the present invention are helpful to solve the problem of crystallization of ultra-thin films.

Abstract translation: 本发明通过与优化的热处理技术结合，将特定量的SiO 2成分掺入到高K栅介质材料HfO 2中，形成具有立方相或四方相的Hf1-xSixOy，从而获得高K栅极电介质 具有较大带隙，较高K值和高热稳定性的薄膜材料。 此外，本发明中提出的高K栅介质薄膜及其制备方法有助于解决超薄膜结晶的问题。

公开(公告)号：US20120080792A1

公开(公告)日：2012-04-05

申请号：US13143507

申请日：2011-02-17

Applicant: Chao Zhao

Inventor： Chao Zhao

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug.

Abstract translation: 提供一种用于形成金属中间层通孔的方法，包括：在第一电介质层上形成晶种层和嵌入第一介电层中的第一金属层; 在种子层上形成掩模图案以暴露覆盖一些第一金属层的种子层的一部分; 在种子层的暴露部分上生长第二金属层; 去除掩模图案和携带掩模图案的种子层的一部分以暴露第二金属层的侧壁，第一金属层和第一介电层的一部分; 在侧壁上形成绝缘阻挡层，第一金属层和第一介电层的部分。 还提供了一种用于形成金属互连线的方法。 他们都可以抑制空洞的发生。 还提供了一种金属互连结构，其包括接触插塞，通孔和金属互连线，其中通孔形成在金属互连线，金属栅极和/或接触插塞上。

公开(公告)号：US09419108B2

公开(公告)日：2016-08-16

申请号：US14406904

申请日：2012-08-17

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract translation: 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

Abstract translation: 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US08748983B2

公开(公告)日：2014-06-10

申请号：US13380828

申请日：2011-08-12

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L27/12 ,  H01L21/70

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract translation: 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。