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98 条记录 (耗时 0.034 秒)

    Dummy error addition circuit
    33.
    发明授权
    Dummy error addition circuit 失效
    虚假误差加法电路

    公开(公告)号：US06772378B1

    公开(公告)日：2004-08-03

    申请号：US09807029

    申请日：2001-04-09

    申请人： Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

    发明人： Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

    IPC分类号： G06F1100

    CPC分类号： H04L1/00 ,  H04L1/0003 ,  H04L1/241

    摘要： A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.

    摘要翻译： 一种用于向正交调制符号数据添加虚拟错误的虚拟错误添加电路，其中基于指定的误码率的值被加载以对计数器（11）计数时钟信号，计数器（11）的载波存储输出 当存储与计数器（11）的计数值一致的数据被识别为误差脉冲时，从PN比较电路（3）输出来自移位寄存器（22）中的PN数据发生器（21）的位选择器（40） 在接收到错误脉冲并基于PN数据生成器（41）的输出时，随机地选择在正交调制数据中添加错误的位，例如 基于比特误码率的间隔的PSK调制符号数据和从正交调制数据中选择的比特在比特反相电路（5）中反转，从而输出错误。

    De-interleave circuit
    34.
    发明授权
    De-interleave circuit 有权
    去交错电路

    公开(公告)号：US06748033B1

    公开(公告)日：2004-06-08

    申请号：US09743718

    申请日：2001-01-16

    申请人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

    发明人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

    IPC分类号： H04L2706

    CPC分类号： H03M13/276 ,  H03M13/2735 ,  H03M13/2785

    摘要： To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory (4) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe.

    摘要翻译： 提供用于BS数字广播接收机的解交织电路。 解交织电路具有较少的存储器。 地址数据生成器（3）以去交织顺序将地址数据（A）提供给解交织存储器（4）。 从由地址数据（A）指定的解交织存储器（4）中的地址位置读取每个主信号，并且将以下主信号交织并写入存储器的该地址位置。 结果，解交织存储器（4）仅需要一个超帧的空间。

    BS digital broadcast receiver
    35.
    发明授权
    BS digital broadcast receiver 有权
    BS数字广播接收机

    公开(公告)号：US06714596B1

    公开(公告)日：2004-03-30

    申请号：US09582228

    申请日：2000-07-21

    申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

    发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

    IPC分类号： H04L2302

    CPC分类号： H04L1/0052 ,  H04L1/0054 ,  H04L1/006 ,  H04L27/2332 ,  H04L2027/0032 ,  H04L2027/0057

    摘要： A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder 6. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder 7. Upper four bits of phase error data are searched from a phase error table 31 for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits 81 to 84 by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit 9. A code TCD2 determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit 10.

    摘要翻译： 没有8PSK解映射器的BS数字广播接收机和用于网格编码的较少数量的延迟电路。 基于绝对相位基带解调信号的接收信号点位置的QPSK基带信号由维特比解码器6进行维特比解码。维特比解码器的输出由卷积编码器7进行卷积重新编码。高四位 根据0度与相位误差检测接收信号点位置的相位之间的相位差，从用于载波再现的相位误差表31中搜索相位误差数据。 延迟电路81至84通过维特比解码所花费的时间和对卷积编码所花费的时间的总和来延迟高四位。 延迟的输出被去映射值转换电路9解映射。从解映射的输出和卷积编码输出确定的代码TCD2作为从MSB代码判断/错误检测电路10的格状8PSK解码输出的MSB输出。

    Received-signal absolute phasing apparatus of receiver
    36.
    发明授权
    Received-signal absolute phasing apparatus of receiver 有权
    接收机的接收信号绝对定相装置

    公开(公告)号：US06683921B1

    公开(公告)日：2004-01-27

    申请号：US09581509

    申请日：2000-06-16

    申请人： Kenichi Shiraishi ,  Akihiro Horii

    发明人： Kenichi Shiraishi ,  Akihiro Horii

    IPC分类号： H03D322

    CPC分类号： H04L27/22 ,  H04L27/2273

    摘要： When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector (16A) of a demodulating circuit (1A) reads high-order three bits &Dgr;&phgr;(3) of phase error data corresponding to I and Q symbol streams out of one phase error table (15-1) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit (8A) detects phase rotation angles of portions corresponding to bits (1) and (0) of a frame-synchronizing signal of a received symbol stream from the &Dgr;&phgr;(3) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper (7) to make the remapper perform absolute phasing. The selector (16A) reads phase error data corresponding to a received symbol stream out of a phase error table corresponding to a modulation system and a phase rotation angle identified by a transmission-configuration identifying circuit (9), outputs the phase error data to a D/A converter (17), corrects a phase of a reference carrier wave for orthogonal detection, and makes a received-signal point become a constant phase for a transmitted-signal point.

    摘要翻译： 当接收到对BPSK，QPSK和8PSK进行PSK调制的复用波开始时，解调电路（1A）的选择器（16A）读取对应于I的相位误差数据的高阶三位Deltaphi（3） 和用于每个调制系统提供的相位误差表和每个相位旋转角度的BPSK的一个相位误差表（15-1）中的Q个符号流。 接收信号相位旋转角度检测电路（8A）检测来自Deltaphi（3）的接收符号流的帧同步信号的与位（1）和（0）相对应的部分的相位旋转角，并且 I符号流并将相位旋转角度输出到再映射器（7），以使再映射器执行绝对定相。 选择器（16A）从对应于由发送配置识别电路（9）识别的调制系统和相位旋转角度的相位误差表读出与接收到的符号流相对应的相位误差数据，将相位误差数据输出到 D / A转换器（17），校正用于正交检测的参考载波的相位，并且使接收信号点成为发送信号点的恒定相位。

    Signal point arrangement dispersion calculation circuit
    37.
    发明授权
    Signal point arrangement dispersion calculation circuit 有权
    信号点布置色散计算电路

    公开(公告)号：US06643335B1

    公开(公告)日：2003-11-04

    申请号：US09463222

    申请日：2000-01-21

    申请人： Akihiro Horii ,  Kenichi Shiraishi

    发明人： Akihiro Horii ,  Kenichi Shiraishi

    IPC分类号： H04L2722

    CPC分类号： H04L27/22

    摘要： A signal point arrangement dispersion calculation circuit whose circuit scale is small. The phase of a demodulation baseband signal is turned by a 22.5° turning remapper (3) at a speed twice the speed of the symbol rate of the demodulation baseband signal. The signal point position of the demodulation baseband signal is found by a signal point arrangement conversion circuit (73) in accordance with the demodulation baseband signal and the baseband signal whose phase is turned by a phase turning circuit. The signal point arrangement of the demodulation baseband signal is converted into the position of the first quadrant in accordance with the found signal point position from the demodulation baseband signal and the baseband signal whose phase is turned 45° by the two successive rotations made by the 22.5° turning remapper (3), and the dispersion is obtained in accordance with the baseband signal whose signal point arrangement is converted.

    摘要翻译： 电路规模小的信号点排列色散计算电路。 解调基带信号的相位以解调基带信号的符号速率的两倍的速度转动22.5°的转换再映射器（3）。 解调基带信号的信号点位置由信号点配置变换电路（73）根据解调基带信号和相位由相位转向电路转向的基带信号求出。 解调基带信号的信号点布置根据来自解调基带信号的所找到的信号点位置和相位为45°的基带信号，由22.5的两次连续转动转换成第一象限的位置 °转动再映射器（3），并且根据其信号点排列被转换的基带信号获得色散。

    Thermally transferred sheet
    38.
    发明授权
    Thermally transferred sheet 失效
    热转印片材

    公开(公告)号：US06362131B1

    公开(公告)日：2002-03-26

    申请号：US09496156

    申请日：2000-02-01

    申请人： Akihiro Horii ,  Tetsuo Kozumi ,  Masayoshi Isago ,  Hirokazu Okada ,  Masataka Mizoguchi

    发明人： Akihiro Horii ,  Tetsuo Kozumi ,  Masayoshi Isago ,  Hirokazu Okada ,  Masataka Mizoguchi

    IPC分类号： B41M5035

    CPC分类号： B41M5/5254 ,  B41M2205/32 ,  Y10S428/913 ,  Y10S428/914 ,  Y10T428/31855

    摘要： A receiver paper used in combination with a thermally transferrable sheet, such as an ink ribbon, in which a laminated layer of the thermally transferrable sheet can be positively transferred, with the receiver paper exhibiting superior running performance and resistance to blocking to enable a picture of high quality and high resolution to be produced. To this end, there is provided a receiver paper made up of substrate and a dye reception layer formed on the substrate. The dye reception layer contains a copolymer of a compound having a pre-set chemical formula and another monomer.

    摘要翻译： 与可转印片材的可热转印片材（例如墨带）组合使用的接收纸，其中可热转印的可热转印片材的层压层与接收纸具有优异的运行性能和阻挡性，从而能够 高质量和高分辨率的生产。 为此，提供了由基板和形成在基板上的染料接收层构成的接收纸。 染料接收层含有具有预定化学式的化合物和另一种单体的共聚物。