公开(公告)号：US06519294B1

公开(公告)日：2003-02-11

申请号：US09743719

申请日：2001-01-16

申请人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

IPC分类号： H03K900

CPC分类号： H04L1/007 ,  H03M13/15 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0065 ,  H04L1/0072 ,  H04L1/0075 ,  H04L2001/0093 ,  H04N5/4401 ,  H04N19/89 ,  H04N21/4382

摘要： A digital broadcasting receiver in which one decoder decodes both Reed-Solomon codes for TMCC and Reed-Solomon codes of an MPEG2-TS packet of a main signal. The received data is divided into a main signal and a TMCC signal. When the separated main signal is subjected to deinterleaving by a deinterleaving circuit (503), the burst symbol signal is eliminated, and the TMCC signal separated subsequent to the main signal in the last frame of a superframe is added by a selector (509). The received data to which the TMCC signal is added is decoded by a basic Reed-Solomon code decoder (510) so as to carry out the error correction of the main signal and the TMCC signal.

摘要翻译： 一种数字广播接收机，其中一个解码器解码用于TMCC的Reed-Solomon码和主信号的MPEG2-TS分组的Reed-Solomon码。 接收的数据被分为主信号和TMCC信号。 当分离的主信号经由去交织电路（503）进行去交织时，消除突发符号信号，并且通过选择器（509）添加在超帧的最后一帧中的主信号之后分离的TMCC信号。 加上TMCC信号的接收数据由基本的里德 - 所罗门码解码器（510）解码，以便执行主信号和TMCC信号的纠错。

公开(公告)号：US06697440B1

公开(公告)日：2004-02-24

申请号：US09622062

申请日：2000-08-25

申请人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii ,  Shoji Matsuda

发明人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H03D322

CPC分类号： H04L27/2273 ,  H04L7/04 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0095

摘要： A small scale circuit can be realized. A timing circuit 30 detects a burst symbol signal period from outputs I and Q of a demodulating circuit 1A for orthogonally detecting a received signal obtained by time-multiplexing digital signals by BPSK, QPSK, and 8PSK modulation. A pattern regeneration circuit 40 outputs the same PN code pattern as on a transmission side. Inverting circuits 13 and 14 output I, Q as RI, RQ for a bit ‘0’ of a PN code pattern, and −I, −Q as RI, RQ for a bit ‘1’. A phase error table 15A contains a phase error between the phase of a received signal point as an output of the inverting circuits 13 and 14 and an absolute phase only for a first quadrant of RI, RQ. A phase error detecting processing circuit 16A reads the phase error data corresponding to the absolute value of RI, RQ, and adjusts the data into the data depending on the current quadrant of the RI, RQ. A carrier regeneration circuit 10A amends the phase of a reference carrier for use in orthogonal detection such that an adjusted phase error data indicates zero.

摘要翻译： 可以实现小规模电路。 定时电路30从解调电路1A的输出I和Q检测突发符号信号周期，以正交检测通过BPSK，QPSK和8PSK调制对数字信号进行时分复用而获得的接收信号。 模式再生电路40输出与发送侧相同的PN码模式。 反相电路13和14输出I，Q作为RI，RQ表示PN码模式的位0，-I，-Q作为RI，RQ表示位1。 相位误差表15A包含作为反相电路13和14的输出的接收信号点的相位与仅针对RI，RQ的第一象限的绝对相位之间的相位误差。 相位误差检测处理电路16A读取对应于RI绝对值RQ的相位误差数据，并且根据RI的当前象限RQ将数据调整为数据。 载波再生电路10A修正用于正交检测的参考载波的相位，使得调整的相位误差数据表示为零。

公开(公告)号：US06772378B1

公开(公告)日：2004-08-03

申请号：US09807029

申请日：2001-04-09

申请人： Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

发明人： Kenichi Ishihara ,  Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

IPC分类号： G06F1100

CPC分类号： H04L1/00 ,  H04L1/0003 ,  H04L1/241

摘要： A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.

摘要翻译： 一种用于向正交调制符号数据添加虚拟错误的虚拟错误添加电路，其中基于指定的误码率的值被加载以对计数器（11）计数时钟信号，计数器（11）的载波存储输出 当存储与计数器（11）的计数值一致的数据被识别为误差脉冲时，从PN比较电路（3）输出来自移位寄存器（22）中的PN数据发生器（21）的位选择器（40） 在接收到错误脉冲并基于PN数据生成器（41）的输出时，随机地选择在正交调制数据中添加错误的位，例如 基于比特误码率的间隔的PSK调制符号数据和从正交调制数据中选择的比特在比特反相电路（5）中反转，从而输出错误。

公开(公告)号：US06748033B1

公开(公告)日：2004-06-08

申请号：US09743718

申请日：2001-01-16

申请人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Soichi Shinjo ,  Akihiro Horii

IPC分类号： H04L2706

CPC分类号： H03M13/276 ,  H03M13/2735 ,  H03M13/2785

摘要： To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory (4) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe.

摘要翻译： 提供用于BS数字广播接收机的解交织电路。 解交织电路具有较少的存储器。 地址数据生成器（3）以去交织顺序将地址数据（A）提供给解交织存储器（4）。 从由地址数据（A）指定的解交织存储器（4）中的地址位置读取每个主信号，并且将以下主信号交织并写入存储器的该地址位置。 结果，解交织存储器（4）仅需要一个超帧的空间。

公开(公告)号：US06714596B1

公开(公告)日：2004-03-30

申请号：US09582228

申请日：2000-07-21

申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

IPC分类号： H04L2302

CPC分类号： H04L1/0052 ,  H04L1/0054 ,  H04L1/006 ,  H04L27/2332 ,  H04L2027/0032 ,  H04L2027/0057

摘要： A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder 6. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder 7. Upper four bits of phase error data are searched from a phase error table 31 for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits 81 to 84 by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit 9. A code TCD2 determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit 10.

摘要翻译： 没有8PSK解映射器的BS数字广播接收机和用于网格编码的较少数量的延迟电路。 基于绝对相位基带解调信号的接收信号点位置的QPSK基带信号由维特比解码器6进行维特比解码。维特比解码器的输出由卷积编码器7进行卷积重新编码。高四位 根据0度与相位误差检测接收信号点位置的相位之间的相位差，从用于载波再现的相位误差表31中搜索相位误差数据。 延迟电路81至84通过维特比解码所花费的时间和对卷积编码所花费的时间的总和来延迟高四位。 延迟的输出被去映射值转换电路9解映射。从解映射的输出和卷积编码输出确定的代码TCD2作为从MSB代码判断/错误检测电路10的格状8PSK解码输出的MSB输出。

公开(公告)号：US06700940B1

公开(公告)日：2004-03-02

申请号：US09581212

申请日：2000-08-15

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H04B1700

CPC分类号： H04L27/2273

摘要： A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.

摘要翻译： 提供即使在以低C / N值进行接收的情况下也能够执行稳定的载波再现的载波再现电路。 利用帧同步定时电路（4）检测解调的已知模式接收信号的接收相位，并且基于检测到的接收相位，具有一个收敛点的绝对相位的相位差表或者具有一个收敛点的相位差表 选择包含在载波再现相位差检测电路（8）中的从绝对相位旋转180°的相位，并且从所选择的相位差表中选择基于从信号点获得的相位之间的相位差的输出 获得接收信号和相位收敛点的位置，从而通过经由AFC电路（10）经历再现的载波频率控制来实现载波再现，使得从信号点位置获得的相位与相位收敛点一致。

公开(公告)号：US06639951B1

公开(公告)日：2003-10-28

申请号：US09554689

申请日：2000-05-18

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H04L2714

CPC分类号： H04L27/2332 ,  H04L7/04 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0095

摘要： A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter (7) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit (6) depending on a BPSK signal of a known pattern. A phase error detector (8) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter (7). The phase error voltage is passed through a carrier filter (9), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

摘要翻译： 提供了一种无需绝对相位电路的数字解调器。 在用于数字广播接收机的数字解调器中，接收不同类型调制的数字时分多路复用信号，根据反相器（7）根据反相指令信号“0”或“1”选择性地将解调的基带信号反相， 根据已知图案的BPSK信号从反转判定电路（6）输出。 用于载波再现的相位误差检测器（8）基于从逆变器（7）输出的解调的基带信号的信号点的绝对相位和相位之间的相位差来确定相位误差电压。 相位误差电压通过包括低通滤波器的载波滤波器（9），以控制载波频率，使得载波再现可以在信号点处的相位与相位收敛点一致。

公开(公告)号：US06813321B1

公开(公告)日：2004-11-02

申请号：US09582229

申请日：2000-07-21

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Yuichi Iwadate ,  Kazuhiko Shibuya ,  Fumiaki Minematsu ,  Shigeyuki Itoh ,  Tomohiro Saito ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Yuichi Iwadate ,  Kazuhiko Shibuya ,  Fumiaki Minematsu ,  Shigeyuki Itoh ,  Tomohiro Saito ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H03D322

CPC分类号： H04L27/2273 ,  H04L7/042 ,  H04L27/0014 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0077 ,  H04L2027/0095

摘要： A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit 6 generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit 7 has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter 8 according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit 6, the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

摘要翻译： 提供了不需要绝对定相电路的数字解调器。 已知模式BPSK信号发生电路6与接收的数字调制波中的已知模式BPSK信号同步地产生与接收的数字调制波中已知模式BPSK信号相同的已知模式BPSK信号，载波再现 相位误差检测电路7具有相位误差表，其中解调基带信号的信号点位置中的参考相位之一成为会聚点，相位误差电压对应于从信号点位置确定的相位之间的相位误差 通过根据从已知模式BPSK信号发生电路6输出的已知模式BPSK信号启用控制载波再现环路滤波器8，发送解调基带信号和相位收敛点，平滑相位误差电压 并且在根据平滑输出控制再现载波的频率的同时执行载波再现，使得si中的相位 点位置与相位收敛点一致。

公开(公告)号：US06625239B1

公开(公告)日：2003-09-23

申请号：US09581259

申请日：2000-06-27

申请人： Kenichi Shiraishi ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Akihiro Horii

IPC分类号： H04L700

CPC分类号： H04L27/22 ,  H04L7/042

摘要： I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8 PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on, I-Q phase plane by &pgr;/4, 2&pgr;/4, and 3&pgr;/4 counterclockwise. When a pattern having is a difference of several bits at most from a frame-synchronizing signal is captured from B0 to B3 by first comparing circuits 60 to 63 and thereafter, a pattern having a difference of several bits at most from a superframe-identifying signal is captured by second comparing circuits 64 to 67 after a predetermined certain time, a frame-synchronizing-signal-capturing-signal generating circuit (90) outputs a frame-synchronizing-signal capturing signal (SYN).

摘要翻译： I和Q符号流从接收到的PSK调制信号解调，其中分别具有20符号长度和8个PSK调制数字信号的BPSK调制帧同步信号和超帧识别信号是时间 由解调电路（1）复用。 根据通过旋转基本BPSK标准边界线和接收信号点与Q轴相同的基本标准边界线获得的标准边界线，由BSPK解映射器（3）生成BPSK去映射比特流B0至B3 在IQ相平面上以pi / 4,2pi / 4和3pi / 4为逆时针方向。 当通过第一比较电路60至63以及其后，从B0到B3捕获具有与帧同步信号最多的几个比特的模式的模式，此后，具有与超帧识别信号最多数位差异的模式 在预定的特定时间之后由第二比较电路64至67捕获，帧同步信号捕获信号产生电路（90）输出帧同步信号捕获信号（SYN）。

公开(公告)号：US06526107B1

公开(公告)日：2003-02-25

申请号：US09530962

申请日：2000-07-12

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii

IPC分类号： H04L700

CPC分类号： H04J3/0605 ,  H04J3/0608 ,  H04L7/0083 ,  H04L27/22

摘要： There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.

摘要翻译： 提供了一种在低C / N时接收帧同步时稳定地获取帧同步而不进行伪同步锁定的同步获取电路。 接收帧的同步模式由帧同步检测电路2检测。通过帧同步电路5将接收帧的同步模式的比特与发送侧的帧同步模式的位进行比较，以获得数字 一致的位。 当获得的每帧的比特数等于或大于相关检测值时，认为帧同步被检测。