利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.136 秒)

    Dopant activation in doped semiconductor substrates
    35.
    发明授权
    Dopant activation in doped semiconductor substrates 失效
    掺杂半导体衬底中的掺杂剂活化

    公开(公告)号：US07989366B2

    公开(公告)日：2011-08-02

    申请号：US11844810

    申请日：2007-08-24

    申请人： Jeffrey C. Munro ,  Srinivas D. Nemani ,  Young S. Lee ,  Marlon Menezes ,  Christopher Dennis Bencher ,  Vijay Parihar

    发明人： Jeffrey C. Munro ,  Srinivas D. Nemani ,  Young S. Lee ,  Marlon Menezes ,  Christopher Dennis Bencher ,  Vijay Parihar

    IPC分类号： H01L21/00

    CPC分类号： H01L21/268 ,  H01L21/26513

    摘要： Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.

    摘要翻译： 公开了用于激活掺杂半导体衬底中的掺杂剂的方法。 碳前体流入其中设置掺杂半导体衬底的衬底处理室。 在基板处理室中由碳前体形成等离子体。 用等离子体沉积在衬底上的碳膜。 在沉积低于500℃的碳膜的同时保持基板的温度。沉积的碳膜暴露于电磁辐射小于10ms的时间段，并且在电磁波包括的波长处具有大于0.3的消光系数 辐射。

    Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface
    37.
    发明授权
    Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface 失效
    在栅极绝缘体 - 硅界面处形成具有最小界面陷阱密度的离子后植入物动态表面退火工艺的PN结的方法

    公开(公告)号：US07659187B2

    公开(公告)日：2010-02-09

    申请号：US11735947

    申请日：2007-04-16

    申请人： Philip Allan Kraus ,  Vijay Parihar

    发明人： Philip Allan Kraus ,  Vijay Parihar

    IPC分类号： H01L21/425

    CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L21/823418 ,  H01L29/66575

    摘要： A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the bulk of the wafer to an elevated temperature over 350 degrees C. but below a temperature at which the dopant atoms tend to cluster. Meanwhile, an intense line beam is produced having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength. This line beam is scanned across the surface of the heated wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) an extremely shallow below-surface depth. During the scanning step, the surface state density at the interface between the semiconductor material and the gate insulator is minimized by continuing to maintain the temperature of the bulk of the wafer outside of the moving localized region at said elevated temperature, while maintaining the rate at which the line beam is scanned along the fast axis at a rate in excess of 300 mm/sec.

    摘要翻译： 在晶片上形成晶体管的方法包括在晶片的表面上的栅极绝缘体上形成栅极，并将离子注入掺杂杂质原子放入晶片中以形成在每个栅极的相对侧对准的源区和漏区。 然后通过将晶片的大部分预热至350℃以上的高温但低于掺杂剂原子倾向于聚集的温度来退火晶片。 同时，产生沿着来自所选波长的相干CW激光器阵列的快轴具有窄尺寸的强线束。 该线束沿加热晶片的表面沿着快轴的方向扫描，以加热直到晶片的熔化温度附近的峰值表面温度，晶片表面上的移动局部区域具有 （a）对应于窄梁宽度的宽度和（b）非常浅的下表面深度。 在扫描步骤期间，通过在所述升高的温度下继续将晶片的主体的温度保持在移动的局部区域的外部，同时将速率保持在该范围内，使半导体材料和栅极绝缘体之间的界面处的表面状态密度最小化 其中线束以快速轴线以超过300mm / sec的速率扫描。

    RADIANT ANNEAL THROUGHPUT OPTIMIZATION AND THERMAL HISTORY MINIMIZATION BY INTERLACING
    38.
    发明申请
    RADIANT ANNEAL THROUGHPUT OPTIMIZATION AND THERMAL HISTORY MINIMIZATION BY INTERLACING 有权
    辐射式退火优化和热历史最小化

    公开(公告)号：US20090261078A1

    公开(公告)日：2009-10-22

    申请号：US12240035

    申请日：2008-09-29

    申请人： KAI MA ,  Abhilash J. Mayur ,  Vijay Parihar

    发明人： KAI MA ,  Abhilash J. Mayur ,  Vijay Parihar

    IPC分类号： B23K26/08

    CPC分类号： H01L21/268 ,  B23K26/0006 ,  B23K26/0876 ,  B23K2103/56

    摘要： The time between illumination of adjacent zones of a workpiece edge is extended by a long cool-down period or delay, by interlacing a radiation beam scanning pattern. During the cool-down period, the beam successively scans (along the fast axis) two rows separated by about half the wafer diameter, and travels back and then forth (along the slow axis) across the distance between the two rows, while the radiation beam source continuously generates the beam.

    摘要翻译： 工件边缘的相邻区域的照射之间的时间通过交织辐射束扫描图案而延长长时间的冷却周期或延迟。 在冷却期间，光束连续地扫描（沿着快轴）两行，间隔大约一半的晶片直径，并且沿着两行之间的距离向后（和沿着慢轴）行进，而辐射 光束源连续生成光束。

    Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer
    40.
    发明授权
    Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer 失效
    用低温HDPCVD工艺的注入掺杂剂的动态表面退火，用于沉积高消光系数光吸收层

    公开(公告)号：US07588990B2

    公开(公告)日：2009-09-15

    申请号：US11692778

    申请日：2007-03-28

    申请人： Vijay Parihar ,  Christopher Dennis Bencher ,  Rajesh Kanuri ,  Marlon E. Menezes

    发明人： Vijay Parihar ,  Christopher Dennis Bencher ,  Rajesh Kanuri ,  Marlon E. Menezes

    IPC分类号： H01L21/336

    CPC分类号： C23C16/26 ,  C23C14/5813 ,  C23C16/56 ,  H01L21/26513 ,  H01L21/268

    摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber and furnishing a hydrocarbon process gas into the chamber, preferably propylene (C3H6) or toluene (C7H8) or acetylene (C2H2) or a mixture of acetylene and methane (C2H4). The process further includes inductively coupling RF plasma source power into the chamber while and applying RF plasma bias power to the wafer. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired stress (compressive or tensile). We have discovered that at a wafer temperature less than or equal to 475 degrees C., total RF plasma source power of 4000 Watts at about 2 MHz, RF plasma bias power of 2000-3000 Watts at about 13.56 MHz and a chamber pressure in a range of 3 mTorr to 2 Torr, the deposited amorphous carbon layer has a surprising combination of high absorption and high strength and excellent step coverage.

    摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入室中并将烃工艺气体提供到室中，优选丙烯（C 3 H 6）或甲苯（C 7 H 8）或乙炔（C 2 H 2） 或乙炔和甲烷（C2H4）的混合物。 该方法还包括将RF等离子体源功率感应耦合到腔室中，同时将RF等离子体偏置功率施加到晶片。 将晶片偏置电压设定为沉积的无定形碳层具有期望的应力（压缩或拉伸）的水平。 我们已经发现，在晶片温度小于或等于475摄氏度的情况下，在大约2MHz处的4000瓦特的RF射频等离子体源功率，在约13.56MHz的RF等离子体等离子体功率为2000-3000瓦， 3mTorr至2Torr的范围，沉积的非晶碳层具有高吸收和高强度以及优异的台阶覆盖的令人惊奇的组合。