公开(公告)号：US20210125660A1

公开(公告)日：2021-04-29

申请号：US17008452

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi MAEJIMA

IPC: G11C11/4094 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4074 ,  G11C5/06 ,  G11C7/10

Abstract: A semiconductor storage device includes a memory unit and a circuit unit bonded to the memory unit. The memory unit includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines. The circuit unit includes a sense amplifier unit including a first wire, a third bonding metal connected with the first wire and opposed to the first bonding metal, and a fourth bonding metal connected with the first wire and opposed to the second bonding metal.

公开(公告)号：US20210118862A1

公开(公告)日：2021-04-22

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20250149098A1

公开(公告)日：2025-05-08

申请号：US19014791

申请日：2025-01-09

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/26 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.

公开(公告)号：US20250147702A1

公开(公告)日：2025-05-08

申请号：US19018307

申请日：2025-01-13

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G06F3/06 ,  G06N3/08 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile semiconductor memory includes a first memory string, a first interconnect coupled to one end of the first memory string, a second interconnect coupled to another end of the first memory string, a first circuit configured to control the first interconnect in accordance with first data, and a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.

公开(公告)号：US20250014643A1

公开(公告)日：2025-01-09

申请号：US18740905

申请日：2024-06-12

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/26 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device according to one embodiment includes includes bit lines, strings, first and second wirings, a word line, and a sequencer. Each of the strings has one end coupled to the bit lines. Each of the strings includes a memory cell, and first and second transistors coupled in series. The first wiring is coupled to the first transistor of each of the strings. The second wiring is coupled to the second transistor of each of the strings. The word line is coupled to the memory cell of each of the strings. The sequencer is configured to, in a read operation of N bytes in which the word line is selected, apply a first voltage to one of the first wiring line and the second wiring line, and apply a second voltage higher than the first voltage to the other of the first wiring line and the second wiring line.

公开(公告)号：US20240282391A1

公开(公告)日：2024-08-22

申请号：US18438636

申请日：2024-02-12

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor memory device includes, a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series, a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series, a word line, a first selection gate line, a second selection gate line, a third selection gate line, a fourth selection gate line, a first bit line, and a second bit line. In a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line.

公开(公告)号：US20240105270A1

公开(公告)日：2024-03-28

申请号：US18458891

申请日：2023-08-30

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/26 ,  G11C7/06 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C7/06 ,  G11C16/08 ,  G11C16/3459

Abstract: A semiconductor memory device includes first, second, and third chips. The first chip includes a first memory cell. The second chip includes a second memory cell. The third chip includes a row decoder and a sense amplifier. The first and second memory cells are commonly connected to the row decoder via a first word line. The first and second memory cells are connected to the sense amplifier via first and second bit lines, respectively. The sense amplifier includes a first node selectively connectable to the first and second bit lines. The sense amplifier is configured to sense a voltage at the first node to read data in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data in the second memory cell when the first node is connected to the second bit line.

公开(公告)号：US20230307434A1

公开(公告)日：2023-09-28

申请号：US18203952

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20230307395A1

公开(公告)日：2023-09-28

申请号：US17813812

申请日：2022-07-20

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Masaki UNNO ,  Hiroyuki TAKENAKA ,  Yoshiaki TAKAHASHI ,  Hiroshi MAEJIMA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

公开(公告)号：US20230154536A1

公开(公告)日：2023-05-18

申请号：US17841362

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: According to One embodiment, a semiconductor memory device includes: a first memory cell array; a, second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first lord line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array an the third memory cell array.