公开(公告)号：US08642467B2

公开(公告)日：2014-02-04

申请号：US13348364

申请日：2012-01-11

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

公开(公告)号：US07910474B2

公开(公告)日：2011-03-22

申请号：US12098190

申请日：2008-04-04

申请人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Kazuhiko Endo

发明人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Kazuhiko Endo

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.

摘要翻译： 本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性 及其制造方法。 设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳 和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳含量的高碳浓度膜6b为 在其中设置为上层，由此通过低碳浓度膜6a的存在可以确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘合性，而整个电介质 通过高碳浓度膜6b的存在可以很好地降低常数。

公开(公告)号：US20100224995A1

公开(公告)日：2010-09-09

申请号：US12773493

申请日：2010-05-04

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L23/532

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

公开(公告)号：US07763979B2

公开(公告)日：2010-07-27

申请号：US11534941

申请日：2006-09-25

申请人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Kazuhiko Endo

发明人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Kazuhiko Endo

IPC分类号： H01L25/34

CPC分类号： H01L21/7681 ,  C23C16/30 ,  C23C16/36 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.Furthermore, because the etching selection ratio of SiOC to SiCN as well as that of SiOC to SiC are small, if SiCN or SiC is used as the etching stopper film, the surface of the metal interconnection layer may be oxidized at the time of photoresist removal, which gives rise to a problem of high contact resistance.The present invention relates to an organic film made of one of SiOCH, SiCHN and SiCH that is formed using, as a source, a polyorganosilane whose C/Si ratio is at least 5 or greater and molecular weight is 100 or greater, and a semiconductor device wherein such an organic insulating film is used, and more particularly to a semiconductor device having a trench structure.

摘要翻译： 目前被广泛研究的SiC和SiCN的介电常数分别为4.5〜5左右，SiOC为2.8〜3.0左右。 随着器件尺寸减小引起的互连尺寸和互连间距的进一步小型化，出现了强烈的要求，即应进一步降低介电常数。 此外，由于SiOC与SiCN的蚀刻选择比以及SiOC与SiC的蚀刻选择比小，因此如果使用SiCN或SiC作为蚀刻停止膜，则金属配线层的表面在光刻胶去除时可能被氧化 ，这导致高接触电阻的问题。 本发明涉及使用以C / Si比为5以上且分子量为100以上的聚有机硅烷作为源的SiOCH，SiCHN和SiCH之一构成的有机膜，以及半导体 使用这种有机绝缘膜的装置，更具体地说涉及具有沟槽结构的半导体器件。

公开(公告)号：US07737555B2

公开(公告)日：2010-06-15

申请号：US11647187

申请日：2006-12-29

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

公开(公告)号：US07649258B2

公开(公告)日：2010-01-19

申请号：US11197360

申请日：2005-08-05

申请人： Tatsuya Usami ,  Koichi Ohto

发明人： Tatsuya Usami ,  Koichi Ohto

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76801 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/522 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： Propagation of a crack in a semiconductor device is to be suppressed, thus to protect an element forming region. An interface reinforcing film is provided so as to cover a sidewall of a concave portion that penetrates a SiCN film and a SiOC film formed on a silicon substrate. The interface reinforcing film is integrally and continuously formed with another SiOC film, and includes an air gap.

摘要翻译： 要抑制半导体器件中的裂纹的传播，从而保护元件形成区域。 提供了界面增强膜，以覆盖贯穿SiCN膜的凹部的侧壁和形成在硅基板上的SiOC膜。 界面增强膜与另一SiOC膜一体连续地形成，并且包括气隙。

公开(公告)号：US07473630B2

公开(公告)日：2009-01-06

申请号：US11542212

申请日：2006-10-04

申请人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto

发明人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto

IPC分类号： H01L21/20 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device includes a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device also includes an electric conductor that extends through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is covers side surfaces and a bottom surface of the Cu film 120. An insulating film 116 is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).

摘要翻译： 提供了一种用于抑制在半导体器件中发生的绝缘击穿的技术。 半导体器件包括半导体衬底（未示出），形成在半导体衬底上的层间绝缘膜102和设置在层间绝缘膜102上的多层绝缘膜140.半导体器件还包括延伸穿过 多层绝缘膜140，并且包括Cu膜120和阻挡金属膜118.阻挡金属膜118覆盖Cu膜120的侧表面和底表面。绝缘膜116设置在多层绝缘体 膜140和导电体（即Cu膜120和阻挡金属膜118）。

公开(公告)号：US07391115B2

公开(公告)日：2008-06-24

申请号：US10768676

申请日：2004-02-02

申请人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Kazuhiko Endo

发明人： Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Kazuhiko Endo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.The barrier film (for instance, a second barrier film 6) disposed between the interconnection or the via plug and its overlying interlayer insulating film is made to have a layered structure made of a plurality of films containing silicon and carbon (preferably, silicon, carbon and nitrogen), with different carbon contents, and, in particular, a low-carbon-concentration film 6a with a small carbon content is set to be a lower layer therein and a high-carbon-concentration film 6b with a large carbon content is set to be an upper layer therein, whereby the effectual prevention against the Cu diffusion, a high etching selection ratio and good adhesiveness to the Cu interconnection can be certainly provided by the presence of the low-carbon-concentration film 6a, while the overall dielectric constant can be well reduced by the presence of the high-carbon-concentration film 6b.

摘要翻译： 本发明的目的是提供一种半导体器件，其包括其间的层间绝缘膜的蚀刻选择率高的阻挡膜，对Cu扩散的良好的预防功能，低介电常数和对Cu互连的优异粘合性 及其制造方法。 设置在互连或通孔插塞及其上覆层间绝缘膜之间的阻挡膜（例如，第二阻挡膜6）具有由多个含有硅和碳的膜（优选硅，碳 和氮），具有不同的碳含量，特别是具有小碳含量的低碳浓度膜6a被设定为下层，并且具有大碳的高碳浓度膜6b 含量被设定为上层，由此可以通过低碳浓度膜6a的存在来确定地提供对Cu扩散的有效防止，高的蚀刻选择率和对Cu互连的良好的粘附性，同时 通过存在高碳浓度膜6b可以很好地降低总介电常数。

公开(公告)号：US20070212809A1

公开(公告)日：2007-09-13

申请号：US11750116

申请日：2007-05-17

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L21/76

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

公开(公告)号：US20070182014A1

公开(公告)日：2007-08-09

申请号：US11702074

申请日：2007-02-05

申请人： Tatsuya Usami ,  Koichi Ohto

发明人： Tatsuya Usami ,  Koichi Ohto

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved migration resistance of the interconnect is provided and a diffusion of silicon into the inside of the interconnect is suppressed. A semiconductor device includes a silicon substrate, a first insulating film provided on the silicon substrate and composed of an SiCN film, an SiOC film and an SiO2 film, and a first copper interconnect provided in the first insulating film and essentially composed of a copper-containing metal. An Si—O unevenly distributed layer doped with injected silicon is included in the vicinity of the surface in the inside of the first copper interconnect, and injected atomic silicon at least partially creates Si—O bond.

摘要翻译： 提供了互连的改进的耐迁移电阻，并且抑制了硅扩散到互连的内部。 半导体器件包括硅衬底，设置在硅衬底上并由SiCN膜，SiOC膜和SiO 2膜构成的第一绝缘膜，以及设置在第一绝缘层中的第一铜互连 并且基本上由含铜金属组成。 掺杂有注入硅的Si-O不均匀分布层包含在第一铜互连内部表面附近，并且注入的原子硅至少部分地形成Si-O键。