Forming linked lists using content addressable memory
    32.
    发明授权
    Forming linked lists using content addressable memory 失效
    使用内容可寻址内存形成链表

    公开(公告)号:US06820086B1

    公开(公告)日:2004-11-16

    申请号:US09336046

    申请日:1999-06-18

    IPC分类号: G06F700

    摘要: A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.

    摘要翻译: 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索,可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。

    Computer that selectively forces ordered execution of store and load
operations between a CPU and a shared memory
    33.
    发明授权
    Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory 失效
    选择性地强制执行CPU和共享内存之间的存储和加载操作的计算机

    公开(公告)号:US6079012A

    公开(公告)日:2000-06-20

    申请号:US968923

    申请日:1997-11-06

    摘要: A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

    摘要翻译: 一种计算机装置,其通过程序执行存储或加载操作,所述程序在由程序顺序完成指令的CPU执行时不提供同步。 检测到存储或加载后,CPU会将操作明确地命令到共享内存页面中。 存储操作被排序,使得在共享存储器页面中的所有先前的存储操作完成之前,不执行在共享存储器页面中的新存储。 此外,加载操作被排序,使得来自共享存储器页面的加载操作以程序顺序执行。 该排序通过维护与共享存储器页相关联的进程位和存储器属性位来实现。 当两个位都为真时,将对所有引用共享存储器页面的加载或存储操作进行排序。

    Forming linked lists using content addressable memory
    34.
    发明授权
    Forming linked lists using content addressable memory 失效
    使用内容可寻址内存形成链表

    公开(公告)号:US5995967A

    公开(公告)日:1999-11-30

    申请号:US734003

    申请日:1996-10-18

    IPC分类号: G06F12/02 G06F12/08 G06F17/30

    摘要: A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.

    摘要翻译: 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索,可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。

    Explicit instructions for control of translation lookaside buffers
    36.
    发明授权
    Explicit instructions for control of translation lookaside buffers 失效
    用于控制翻译后备缓冲区的明确说明

    公开(公告)号:US5060137A

    公开(公告)日:1991-10-22

    申请号:US229750

    申请日:1988-08-03

    IPC分类号: G06F12/10

    CPC分类号: G06F12/1027

    摘要: Explicit instructions are provided that enable software to directly control insertion of information into a translation lookaside buffer (TLB). A first pair of instructions enable information to be inserted into a data TLB and a second pair of instructions enable information to be inserted into an instruction TLB. In each of these pairs, the first instruction inserts the virtual address and the associated physical address. In response to the second instruction of each of these pairs, additional information about that physical page, such as protection information and flags, is inserted.

    摘要翻译: 提供显式指令,使软件能够直接控制信息插入到翻译后备缓冲器(TLB)中。 第一对指令使得能够将信息插入到数据TLB中,并且第二对指令使得能够将信息插入到指令TLB中。 在每个这些对中,第一条指令插入虚拟地址和相关联的物理地址。 响应于这些对中的每一个的第二指令,插入关于该物理页面的附加信息,例如保护信息和标志。

    Cache memory consistency control with explicit software instructions
    38.
    发明授权
    Cache memory consistency control with explicit software instructions 失效
    具有显式软件指令的缓存内存一致性控制

    公开(公告)号:US4713755A

    公开(公告)日:1987-12-15

    申请号:US750381

    申请日:1985-06-28

    IPC分类号: G06F9/38 G06F12/08

    摘要: Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

    摘要翻译: 在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。 系统中的缓存具有两个状态标志,一个有效位和一个脏位,每个信息块都被存储。 操作系统执行选定的缓存控制指令,以确保内存完整性,只要可能会危及完整性。