利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.026 秒)

    Cache memory consistency control with explicit software instructions
    3.
    发明授权
    Cache memory consistency control with explicit software instructions 失效
    具有显式软件指令的缓存内存一致性控制

    公开(公告)号：US4713755A

    公开(公告)日：1987-12-15

    申请号：US750381

    申请日：1985-06-28

    申请人： William S. Worley, Jr. ,  William R. Bryg ,  Allen Baum

    发明人： William S. Worley, Jr. ,  William R. Bryg ,  Allen Baum

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3812 ,  G06F12/0804 ,  G06F12/0837 ,  Y10S707/99934

    摘要： Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.

    摘要翻译： 在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。 系统中的缓存具有两个状态标志，一个有效位和一个脏位，每个信息块都被存储。 操作系统执行选定的缓存控制指令，以确保内存完整性，只要可能会危及完整性。

    Method in a computing system for performing a multiplication
    4.
    发明授权
    Method in a computing system for performing a multiplication 失效
    用于执行乘法的计算系统中的方法

    公开(公告)号：US4947364A

    公开(公告)日：1990-08-07

    申请号：US392177

    申请日：1989-08-09

    申请人： Michael J. Mahon ,  Allen Baum

    发明人： Michael J. Mahon ,  Allen Baum

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5332

    摘要： In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit. Second, for every other bit in the current section that is a "1", a shift-and-add operation is performed by shifting, via the preshifter, the contents of the first register by an amount equal to the number of bit places the bit is to the left of the low order bit of the current section and by adding, via the arithmetic logic unit, the preshifted contents of the first register to the contents of the second register. Third, for every section from the plurality of sections that does not contain low order bits of the first multiplicand, the contents of the first register "n" bits are shifted to the left.

    摘要翻译： 在计算系统中，呈现执行第一被乘数和第二被乘数相乘的方法。 计算系统包括多个寄存器，指令解码器，算术逻辑单元和预定机。 第一被乘数被分成多个等长的部分。 每个部分包括“n”位，其中“n”是大于1的整数。 第二被乘数被放置在来自多个寄存器的第一寄存器中。 来自多个寄存器的第二寄存器被清零。 对于来自多个部分的每个部分，从包含第一乘法的高阶位的第一部分开始，并且进行到包含第一被乘数的低阶位的第一被乘数的最后部分以及以下三个子步骤。 首先，当当前部分的低位位为“1”时，第一寄存器的内容经由算术逻辑单元被添加到第二寄存器的内容。 第二，对于当前部分中的“1”的每个其他位，移位和加法运算是通过预定机器将第一寄存器的内容移位等于位置数 位位于当前部分的低位位置的左侧，并且经由算术逻辑单元将第一寄存器的预定内容相加到第二寄存器的内容。 第三，对于不包含第一被乘数的低位的多个部分的每个部分，第一个寄存器“n”位的内容向左移位。

    Method and apparatus for communication between two or more processing elements
    5.
    发明授权
    Method and apparatus for communication between two or more processing elements 失效
    用于在两个或多个处理元件之间进行通信的方法和装置

    公开(公告)号：US08645959B2

    公开(公告)日：2014-02-04

    申请号：US11095341

    申请日：2005-03-30

    申请人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    发明人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/522

    摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

    摘要翻译： 一种用于在多个程序线程之间执行屏障同步的技术。 更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。

    Trial-and-error multi-bit error correction
    7.
    发明申请
    Trial-and-error multi-bit error correction 失效
    试错多位纠错

    公开(公告)号：US20060174182A1

    公开(公告)日：2006-08-03

    申请号：US11046491

    申请日：2005-01-28

    申请人： Henk Neefs ,  Allen Baum

    发明人： Henk Neefs ,  Allen Baum

    IPC分类号： H03M13/00

    CPC分类号： H03M13/3746 ,  H03M13/09 ,  H03M13/098

    摘要： An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with at least one transaction performed on a unit. A controller controls iterating the generation of the data syndrome.

    摘要翻译： 本发明的实施例是使用试错法进行纠错的技术。 校正子发生器提供根据至少一个纠错参数的选择修改的数据字的数据校正子的产生。 数据字与在一个单元上执行的至少一个事务相关联。 控制器控制迭代数据综合征的产生。

    Live network configuration within a link based computing system
    10.
    发明授权
    Live network configuration within a link based computing system 有权
    基于链路的计算系统中的实时网络配置

    公开(公告)号：US08145732B2

    公开(公告)日：2012-03-27

    申请号：US11284537

    申请日：2005-11-21

    申请人： Mohan J. Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

    发明人： Mohan J. Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

    IPC分类号： G06F15/177 ,  G06F15/173 ,  G06F15/16 ,  G06F11/00 ,  G06F9/44 ,  G06F9/445 ,  H04L12/28 ,  H04B1/38 ,  G06Q10/00 ,  G06Q30/00

    CPC分类号： H04L41/082

    摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.

    摘要翻译： 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。