公开(公告)号：US11887949B2

公开(公告)日：2024-01-30

申请号：US17405812

申请日：2021-08-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh Lo ,  Jian-Syu Lin ,  Yi-Fan Chang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05016 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05095

Abstract: Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

公开(公告)号：US20230343657A1

公开(公告)日：2023-10-26

申请号：US18341957

申请日：2023-06-27

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R31/2896 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/1623

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

公开(公告)号：US11631464B2

公开(公告)日：2023-04-18

申请号：US17178313

申请日：2021-02-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh Lo ,  Kuen-Long Chang

IPC: G11C16/16 ,  G11C16/30 ,  G11C16/34 ,  G11C16/26

Abstract: A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

公开(公告)号：US11631441B2

公开(公告)日：2023-04-18

申请号：US17701044

申请日：2022-03-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Su-Chueh Lo ,  Yung-Feng Lin

IPC: G11C7/10 ,  G06F9/38 ,  G06F9/445 ,  G11C7/22

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

公开(公告)号：US20230085583A1

公开(公告)日：2023-03-16

申请号：US17477229

申请日：2021-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three dimension memory device, such as a three dimensional AND flash memory is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches, and a plurality of source line switches. The memory array has a plurality of memory cell rows respectively coupled to a plurality of source lines and bit lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and second transistors. The first transistors are coupled to a common bit line and the bit line. The second transistors are coupled to a common source line and the source lines. The first transistors are P-type transistors or an N-type transistors with a triple-well substrate, and the second transistors are P-type transistor or an N-type transistors with a triple-well substrate.

公开(公告)号：US11302366B2

公开(公告)日：2022-04-12

申请号：US17070340

申请日：2020-10-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Su-Chueh Lo ,  Yung-Feng Lin

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/445 ,  G06F9/38

Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

公开(公告)号：US20210366793A1

公开(公告)日：2021-11-25

申请号：US16877697

申请日：2020-05-19

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L23/498

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

公开(公告)号：US09940048B2

公开(公告)日：2018-04-10

申请号：US14310502

申请日：2014-06-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0622 ,  G06F3/062 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/1416

Abstract: Methods for protecting data on an integrated circuit including a memory are described. One method includes storing nonvolatile protection codes on the integrated circuit. The nonvolatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in a plurality of sectors of the memory. The method includes storing volatile protection codes on the integrated circuit. The volatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in the plurality of sectors. The method includes blocking modification in a particular sector using circuitry on the integrated circuit when the volatile protection code for the particular sector has the first value, else allowing modification in the particular sector, and setting the volatile protection codes to values of the nonvolatile protection codes in an initialization procedure.

公开(公告)号：US20170358357A1

公开(公告)日：2017-12-14

申请号：US15390823

申请日：2016-12-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Ming-Chih Hsieh

IPC: G11C16/08 ,  G11C16/14

Abstract: A memory device and an operating method thereof are provided. The memory device includes a first memory array, a first row decoder, a first column decoder, a second memory array, a second row decoder and a second column decoder. The first memory array and the second memory array are different type memories and formed in a single memory die of a wafer.

公开(公告)号：US20170351636A1

公开(公告)日：2017-12-07

申请号：US15411731

申请日：2017-01-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Su-Chueh Lo ,  Chun-Yu Liao

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4234 ,  G06F13/1631 ,  G06F13/1673 ,  G06F13/4291

Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.