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    PHYSICAL LAYER SYNCHRONIZATION
    31.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240373379A1

    公开(公告)日：2024-11-07

    申请号：US18225525

    申请日：2023-07-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

    IPC: H04W56/00

    Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

    Scalable Boundary Clock
    32.
    发明公开
    Scalable Boundary Clock 审中-公开

    公开(公告)号：US20230367358A1

    公开(公告)日：2023-11-16

    申请号：US17867779

    申请日：2022-07-19

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ariel Almog ,  Bar Shapira

    IPC: G06F1/12 ,  G06F1/10 ,  G06F1/06

    CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/06

    Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.

    Hardware clock with built-in accuracy check
    35.
    发明授权
    Hardware clock with built-in accuracy check 有权

    公开(公告)号：US11588609B2

    公开(公告)日：2023-02-21

    申请号：US17148605

    申请日：2021-01-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

    IPC: H04W40/20 ,  H04L7/00

    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

    Maintaining consistent quality of service between subnets
    38.
    发明授权
    Maintaining consistent quality of service between subnets 有权
    保持子网之间一致的服务质量

    公开(公告)号：US09197586B2

    公开(公告)日：2015-11-24

    申请号：US13754912

    申请日：2013-01-31

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Ariel Almog ,  Gil Bloch

    IPC: H04L12/851 ,  H04L12/931 ,  H04L12/823 ,  H04L12/725

    CPC classification number: H04L49/604 ,  H04L45/302 ,  H04L47/2441 ,  H04L47/32

    Abstract: Network apparatus includes a plurality of interfaces, which are coupled to a network so as to receive and transmit data packets having respective link-layer headers and network-layer headers. Each link-layer header includes respective source and destination link-layer addresses and a link-layer priority value. Switching and routing logic is configured, responsively to the network-layer headers, to transfer each data packet from a respective ingress interface to a respective egress interface and to modify the source and destination link-layer addresses of the transferred data packet while copying the link-layer priority value from the ingress interface to the egress interface without modification.

    Abstract translation: 网络装置包括多个接口，其耦合到网络，以便接收和发送具有相应链路层报头和网络层报头的数据分组。 每个链路层报头包括相应的源和目的链路层地址和链路层优先级值。 交换和路由逻辑被配置为响应于网络层报头，将每个数据分组从相应的入口接口传送到相应的出口接口，并且在复制链接的同时修改传送的数据分组的源和目的地链路层地址 从入口接口到出口接口的优先级值，无需修改。

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