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    SYSTEM AND METHODS FOR RAMP CONTROL
    32.
    发明公开
    SYSTEM AND METHODS FOR RAMP CONTROL 审中-公开

    公开(公告)号：US20240022257A1

    公开(公告)日：2024-01-18

    申请号：US18095933

    申请日：2023-01-11

    Applicant: Microchip Technology Incorporated

    Inventor： Andreas Reiter ,  Yong Yuenyongsgool ,  Stephen Bowling ,  John Day ,  Alex Dumais ,  Justin Oshea

    IPC: H03M1/56

    CPC classification number: H03M1/56

    Abstract: A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.

    PROGRAMMABLE FAULT VIOLATION FILTER
    33.
    发明公开
    PROGRAMMABLE FAULT VIOLATION FILTER 审中-公开

    公开(公告)号：US20230393923A1

    公开(公告)日：2023-12-07

    申请号：US18096163

    申请日：2023-01-12

    Applicant: Microchip Technology Incorporated

    Inventor： Andreas Reiter ,  Yong Yuenyongsgool ,  Stephen Bowling ,  Alex Dumais ,  Justin Oshea ,  Sankar Rangarajan

    IPC: G06F11/07

    CPC classification number: G06F11/0772 ,  G06F11/0781 ,  G06F11/076

    Abstract: A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

    Automatic Assignment of Device Debug Communication Pins
    34.
    发明申请
    Automatic Assignment of Device Debug Communication Pins 有权

    公开(公告)号：US20220187788A1

    公开(公告)日：2022-06-16

    申请号：US17530633

    申请日：2021-11-19

    Applicant: Microchip Technology Incorporated

    Inventor： Stephen Bowling ,  Manivannan Balu ,  Timothy Phoenix ,  Sankar Rangarajan

    IPC: G05B19/406

    Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

    Fault tolerant clock monitor system
    36.
    发明授权
    Fault tolerant clock monitor system 有权

    公开(公告)号：US10795783B2

    公开(公告)日：2020-10-06

    申请号：US16158471

    申请日：2018-10-12

    Applicant: Microchip Technology Incorporated

    Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

    IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14 ,  H03K5/19

    Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

    ADC SELF-TEST USING TIME BASE AND CURRENT SOURCE
    38.
    发明申请
    ADC SELF-TEST USING TIME BASE AND CURRENT SOURCE 审中-公开

    公开(公告)号：US20190131993A1

    公开(公告)日：2019-05-02

    申请号：US16176170

    申请日：2018-10-31

    Applicant: Microchip Technology Incorporated

    Inventor： James E. Bartling ,  Stephen Bowling

    IPC: H03M1/10

    Abstract: A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the capacitor for a pre-determined amount of time to produce a voltage thereon. This voltage will be proportional to the amount of time that the capacitor was charged. Multiple points on the ADC transfer function can be verified in this self-check procedure simply by varying the amount of time for charging of the capacitor. Relative accuracy among test points may then be easily obtained. Absolute accuracy may be obtained by using an accurate clock reference for the time base, a known current source and capacitor value.

    Fault Tolerant Clock Monitor System
    39.
    发明申请
    Fault Tolerant Clock Monitor System 审中-公开

    公开(公告)号：US20190114235A1

    公开(公告)日：2019-04-18

    申请号：US16158471

    申请日：2018-10-12

    Applicant: Microchip Technology Incorporated

    Inventor： Igor Wojewoda ,  Bryan Kris ,  Stephen Bowling ,  Yong Yuenyongsgool

    IPC: G06F11/16 ,  G06F11/34 ,  G06F11/14

    Abstract: A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

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