公开(公告)号：US12248411B2

公开(公告)日：2025-03-11

申请号：US18144957

申请日：2023-05-09

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Xiangyu Tang ,  Daniel Jerre Hubbard

IPC: G06F13/16 ,  G06F12/0879 ,  G06F13/32

Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

公开(公告)号：US12182046B2

公开(公告)日：2024-12-31

申请号：US18119578

申请日：2023-03-09

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

公开(公告)号：US11544208B2

公开(公告)日：2023-01-03

申请号：US17324172

申请日：2021-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/08 ,  G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

公开(公告)号：US11528015B2

公开(公告)日：2022-12-13

申请号：US17161546

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K19/0185 ,  H03K3/356

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

公开(公告)号：US20210152160A1

公开(公告)日：2021-05-20

申请号：US17161546

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K19/0185 ,  H03K3/356

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, in some implementations, the first reference node and the second reference node may have signals that are inverse to each other.

公开(公告)号：US20210064278A1

公开(公告)日：2021-03-04

申请号：US16552484

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Ali Feiz Zarrin Ghalam

IPC: G06F3/06 ,  G06F12/0802

Abstract: Aspects of the present disclosure provide systems and methods for managing configuration, timing, and power parameters in memory sub-systems through the allocation of an I/O expander at a position between the controller and a drive that comprises a plurality of NAND dies. In particular, a memory controller is coupled to a drive with an I/O expander, and the I/O expander is assigned a LUN address of one or more memory components of the drive. A user or administrator of the host system can generate requests to configure target features of memory components of the drive by causing the I/O expander to decouple portions of the drive to provide a logical pathway between the memory controller and one or more memory components through reference to the corresponding LUN addresses.

公开(公告)号：US20200343880A1

公开(公告)日：2020-10-29

申请号：US16392352

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ali Feiz Zarrin Ghalam ,  Luigi Pilolli ,  Myung Gyoo Won

IPC: H03K3/017 ,  H03K3/356 ,  H03K19/0185

Abstract: Disclosed are level shifters and methods of performing level shifting. In one embodiment, a level shifter is disclosed comprising an input, cross-coupled/latch circuitry, a first reference node, a second reference node, and output circuitry coupled between the cross-coupled/latch circuitry and an output, wherein the output circuitry sets the output signal to high based on rising edge of a second reference node and sets the output signal to low based on the rising edge of the first reference node. Further, the first reference node and the second reference node are symmetric nodes having signals that are inverse to each other.

公开(公告)号：US10714160B2

公开(公告)日：2020-07-14

申请号：US16531244

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/04 ,  G11C8/18 ,  G11C8/06 ,  G11C8/04

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US10410698B2

公开(公告)日：2019-09-10

申请号：US15834315

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/04 ,  G11C8/18 ,  G11C8/06 ,  G11C16/04

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US20180292990A1

公开(公告)日：2018-10-11

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0802

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.