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公开(公告)号：US20240053922A1
公开(公告)日：2024-02-15
申请号：US17818922
申请日：2022-08-10
Applicant: Micron Technology, Inc.
Inventor： Deping He
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0652 , G06F3/0619 , G06F3/0679
Abstract: Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.
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公开(公告)号：US11721398B2
公开(公告)日：2023-08-08
申请号：US17502497
申请日：2021-10-15
Applicant: Micron Technology, Inc.
Inventor： Deping He , Jingyuan Miao
CPC classification number: G11C16/26 , G11C11/5642 , G11C11/5671
Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.
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公开(公告)号：US11709617B2
公开(公告)日：2023-07-25
申请号：US16997055
申请日：2020-08-19
Applicant: Micron Technology, Inc.
Inventor： Qing Liang , Mingke Yu , Deping He
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0659 , G06F3/0673
Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.
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公开(公告)号：US11693769B2
公开(公告)日：2023-07-04
申请号：US17527776
申请日：2021-11-16
Applicant: Micron Technology, Inc.
Inventor： Qing Liang , Deping He , David Aaron Palmer
CPC classification number: G06F12/0253 , G11C11/1659 , G11C16/10 , G06F12/0246 , G06F2212/7205 , G06F2212/7211 , G11C16/0483 , G11C16/3495 , G11C2211/5641
Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.
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公开(公告)号：US20230052044A1
公开(公告)日：2023-02-16
申请号：US17584034
申请日：2022-01-25
Applicant: Micron Technology, Inc.
Inventor： Deping He , Zhengang Chen
Abstract: Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.
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Patent Agency Ranking
公开(公告)号：US20220253226A1
公开(公告)日：2022-08-11
申请号：US17574044
申请日：2022-01-12
Applicant: Micron Technology, Inc.
Inventor： Deping He , Jonathan S. Parry
IPC: G06F3/06
Abstract: Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.
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公开(公告)号：US11314583B2
公开(公告)日：2022-04-26
申请号：US16996305
申请日：2020-08-18
Applicant: Micron Technology, Inc.
Inventor： Deping He , Qing Liang
Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.
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公开(公告)号：US11287990B2
公开(公告)日：2022-03-29
申请号：US17189502
申请日：2021-03-02
Applicant: Micron Technology, Inc.
Inventor： Qing Liang , Deping He
IPC: G06F3/06 , G11C29/52 , G06F9/4401 , G06F11/10
Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.
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公开(公告)号：US20220058124A1
公开(公告)日：2022-02-24
申请号：US16999985
申请日：2020-08-21
Applicant: Micron Technology, Inc.
Inventor： Deping He , David Aaron Palmer
IPC: G06F12/0811 , G06F12/0882 , G06F12/0891 , G06F11/10 , G06F11/30
Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.
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公开(公告)号：US11188461B2
公开(公告)日：2021-11-30
申请号：US16445769
申请日：2019-06-19
Applicant: Micron Technology, Inc.
Inventor： Qing Liang , Deping He , David Aaron Palmer
Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.
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