公开(公告)号：US20200258943A1

公开(公告)日：2020-08-13

申请号：US16863555

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, memory cells disposed between the first conductive lines and the second conductive lines, each memory cell disposed at an intersection of a first conductive line and a second conductive line, and a passive material between the memory cells and at least one of the first conductive lines and the second conductive lines. Related semiconductor devices and electronic devices are disclosed.

公开(公告)号：US10482954B2

公开(公告)日：2019-11-19

申请号：US15686308

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

Abstract: A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

公开(公告)号：US10424730B2

公开(公告)日：2019-09-24

申请号：US15893106

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Fabio Pellizzer

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.

公开(公告)号：US10424618B2

公开(公告)日：2019-09-24

申请号：US15851112

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

IPC: H01L27/24 ,  H01L45/00

Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

公开(公告)号：US20190287614A1

公开(公告)日：2019-09-19

申请号：US15925536

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

IPC: G11C13/00 ,  H01L23/528

Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

公开(公告)号：US10410718B2

公开(公告)日：2019-09-10

申请号：US16190563

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US10396125B2

公开(公告)日：2019-08-27

申请号：US16045516

申请日：2018-07-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Cristina Casellato ,  Fabio Pellizzer

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1157 ,  H01L45/00 ,  H01L27/24

Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.

公开(公告)号：US10381075B2

公开(公告)日：2019-08-13

申请号：US15842504

申请日：2017-12-14

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Totorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

IPC: G11C13/02 ,  G11C7/00 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

公开(公告)号：US20190206489A1

公开(公告)日：2019-07-04

申请号：US15857188

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Luca Crespi ,  Debayan Mahalanabis ,  Fabio Pellizzer

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2013/0076

Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.

公开(公告)号：US20190123105A1

公开(公告)日：2019-04-25

申请号：US16216100

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L49/02 ,  H01L45/00

Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.