公开(公告)号：US10475656B2

公开(公告)日：2019-11-12

申请号：US15847540

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Matthew S. Thorum ,  Gurtej S. Sandhu

IPC: H01L21/322 ,  H01L21/30 ,  H01L21/67 ,  H01L21/02

Abstract: An example of forming semiconductor devices can include forming a silicon-hydrogen (Si—H) terminated surface on a silicon structure that includes patterned features by exposing the silicon structure to a hydrogen fluoride (HF) containing solution and performing a surface modification via hydrosilylation by exposing the Si—H terminated surface to an alkene and/or an alkyne.

公开(公告)号：US20190319069A1

公开(公告)日：2019-10-17

申请号：US16451938

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sumeet C. Pandey

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic material to the getter seed region, due to a chemical affinity elicited by a getter species. The depletion of the magnetic material enables crystallization of the depleted magnetic material through crystal structure propagation from a neighboring crystalline material, without interference from the now-enriched getter seed region. This promotes high tunnel magnetoresistance and high magnetic anisotropy strength. Also during formation, another diffusive species is transferred from a precursor oxide material to the getter seed region, due to a chemical affinity elicited by another getter species. The depletion of the oxide material enables lower electrical resistance and low damping in the cell structure. Methods of fabrication and semiconductor devices are also disclosed.

公开(公告)号：US20190206723A1

公开(公告)日：2019-07-04

申请号：US15858021

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Ken Tokashiki ,  John A. Smythe ,  Gurtej S. Sandhu

IPC: H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/30655 ,  H01L21/76205 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843

Abstract: Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

公开(公告)号：US20190189424A1

公开(公告)日：2019-06-20

申请号：US15847512

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Matthew S. Thorum ,  Gurtej S. Sandhu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/677

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

公开(公告)号：US10297612B2

公开(公告)日：2019-05-21

申请号：US16020712

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11585 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11514 ,  G11C11/22

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US20190115213A1

公开(公告)日：2019-04-18

申请号：US16207422

申请日：2018-12-03

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L21/033 ,  H01L21/02

Abstract: A semiconductor pitch patterning can include a method comprising forming a first set of spacers on a surface of a substrate. The method can include directionally depositing a mask material on the first set of spacers and on the surface of the substrate. The method can include selectively depositing a second set of spacers on side surfaces of the first set of spacers and a portion of the mask material in contact with the surface of the substrate. The method can include removing portions of the mask material from the surface of the substrate.

公开(公告)号：US20190103406A1

公开(公告)日：2019-04-04

申请号：US16192462

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Martin C. Roberts ,  Gurtej S. Sandhu

IPC: H01L27/108 ,  H01L29/786

Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

公开(公告)号：US10164168B2

公开(公告)日：2018-12-25

申请号：US15187488

申请日：2016-06-20

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Witold Kula ,  Wayne I. Kinney

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10

Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more uniformity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.

公开(公告)号：US10147606B2

公开(公告)日：2018-12-04

申请号：US15452467

申请日：2017-03-07

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu

IPC: H01L21/027 ,  H01L21/768 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  G03F7/039 ,  G03F7/038 ,  G03F7/38

Abstract: A method of forming a semiconductor device structure comprises forming a preliminary structure comprising a substrate, a photoresist material over the substrate, and a plurality of structures longitudinally extending through the photoresist material and at least partially into the substrate. The preliminary structure is exposed to electromagnetic radiation directed toward upper surfaces of the photoresist material and the plurality of structures at an angle non-orthogonal to the upper surfaces to form a patterned photoresist material. The patterned photoresist material is developed to selectively remove some regions of the patterned photoresist material relative to other regions of the patterned photoresist material. Linear structures substantially laterally aligned with at least some structures of the plurality of structures are formed using the other regions of the patterned photoresist material. Additional methods of forming a semiconductor device structure are also described.

公开(公告)号：US10141262B2

公开(公告)日：2018-11-27

申请号：US15975429

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L23/532 ,  H01L21/768

Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.