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公开(公告)号：US12224012B2
公开(公告)日：2025-02-11
申请号：US18127768
申请日：2023-03-29
Applicant: Micron Technology, Inc.
Inventor： Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Sheyang Ning , Jeffrey S. McNeil
Abstract: Described are systems and methods for all level coarse/fine programming of memory cells. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
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公开(公告)号：US12112819B2
公开(公告)日：2024-10-08
申请号：US18376198
申请日：2023-10-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C7/1069 , G11C7/1096 , G11C29/12005 , G11C29/4401
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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公开(公告)号：US20240295970A1
公开(公告)日：2024-09-05
申请号：US18593779
申请日：2024-03-01
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Jeffrey S. McNeil , Tomoko Ogura Iwasaki , Lee-eun Yu , Yeang Meng Hern
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679
Abstract: Control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels. The control logic further causes a series of programming pulses to be applied to the selected wordline, wherein respective memory cells of the set of memory cells are programmed to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude, wherein a second programming pulse in the series of programming pulses has a second magnitude, and wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse increased by a predefined pulse step amount.
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公开(公告)号：US20240221841A1
公开(公告)日：2024-07-04
申请号：US18604276
申请日：2024-03-13
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3404 , G11C16/3481
Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.
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公开(公告)号：US20240005987A1
公开(公告)日：2024-01-04
申请号：US18214080
申请日：2023-06-26
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Jeffrey S. McNeil , Tomoko Ogura Iwasaki
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Control logic in a memory device initiates a program operation including application of a set of programming pulses to a wordline associated with one or more memory cells of a memory array to be programmed to a set of programming levels, where each programming level of the set of programming levels is programmed by each programming pulse. The control logic determines that a program voltage of a programming pulse of the set of programming pulses reaches a maximum program voltage level. In response to the determining, during a subsequent programming pulse following the programming pulse, adjusting a first voltage associated with boosting a pillar voltage, a second voltage applied to a bitline, and a third voltage applied to the wordline to establish a subsequent program voltage of the subsequent programming pulse that is below the maximum program voltage level.
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Patent Agency Ranking
公开(公告)号：US11798647B2
公开(公告)日：2023-10-24
申请号：US17681976
申请日：2022-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C7/1069 , G11C7/1096 , G11C29/12005 , G11C29/4401
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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公开(公告)号：US20230317171A1
公开(公告)日：2023-10-05
申请号：US18127768
申请日：2023-03-29
Applicant: Micron Technology, Inc.
Inventor： Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Sheyang Ning , Jeffrey S. McNeil
CPC classification number: G11C16/10 , G11C16/26 , G11C16/08 , G11C16/24 , G11C16/0483
Abstract: Described are systems and methods for all level coarse/fine programming of memory cells. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
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公开(公告)号：US11749346B2
公开(公告)日：2023-09-05
申请号：US17324538
申请日：2021-05-19
Applicant: Micron Technology, Inc.
Inventor： Tomoko Ogura Iwasaki , Kulachet Tanpairoj , Jianmin Huang , Lawrence Celso Miranda , Sheyang Ning
CPC classification number: G11C16/10 , G11C16/3459 , G11C11/56 , G11C16/0483
Abstract: Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.
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公开(公告)号：US11742036B2
公开(公告)日：2023-08-29
申请号：US17306347
申请日：2021-05-03
Applicant: Micron Technology, Inc.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/28 , G11C16/30
Abstract: Described are systems and methods for reducing maximum programming voltage in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and one or more target bitlines; causing drain-side select gates and source-side select gates of the memory array to be turned off; causing unselected wordlines of the memory array to discharge to a predefined voltage level; and causing one or more programming voltage pulses to be applied to the target wordline.
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公开(公告)号：US20230207019A1
公开(公告)日：2023-06-29
申请号：US18081114
申请日：2022-12-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Lawrence Celso Miranda , Sheyang Ning , Jeffrey S. McNeil , Tomoko Ogura Iwasaki
CPC classification number: G11C16/102 , G11C16/08 , G11C16/24
Abstract: Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
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