公开(公告)号：US11461035B2

公开(公告)日：2022-10-04

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20220199163A1

公开(公告)日：2022-06-23

申请号：US17127358

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Priya Venkataraman ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

公开(公告)号：US12293795B2

公开(公告)日：2025-05-06

申请号：US17897441

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Ekamdeep Singh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/34

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.

公开(公告)号：US12124705B2

公开(公告)日：2024-10-22

申请号：US17848061

申请日：2022-06-23

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Ching-Huang Lu ,  Devin Batutis

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/07

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/002 ,  G06F11/076

Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

公开(公告)号：US20240347084A1

公开(公告)日：2024-10-17

申请号：US18755033

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

公开(公告)号：US12057190B2

公开(公告)日：2024-08-06

申请号：US17897438

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C16/10 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

公开(公告)号：US20240256142A1

公开(公告)日：2024-08-01

申请号：US18420491

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Pitamber Shukla ,  Zhongyuan Lu ,  Niccolo' Righetti

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for managing partially programmed blocks are described. Based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. Based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.

公开(公告)号：US20240194270A1

公开(公告)日：2024-06-13

申请号：US18528337

申请日：2023-12-04

Applicant: Micron Technology, Inc.

Inventor： Qun Su ,  Pitamber Shukla ,  Ryan Hrinya ,  Fulvio Rori ,  Jose Nino N. Monje

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08

Abstract: A method includes determining that a first group of word lines associated with a block of memory cells are in a programmed state and determining that a second group of word lines associated with the block of memory cells are in an unprogrammed state. The method further includes applying a first debiasing voltage to the first group of word lines based on the determination that the first group of word lines are in the programmed state and applying a second debiasing voltage to the second group of word lines based on the determination that the second group of word lines are in the unprogrammed state.

公开(公告)号：US11967386B2

公开(公告)日：2024-04-23

申请号：US17747761

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Bin Wang ,  Pitamber Shukla ,  Scott A. Stoller

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/102

Abstract: An apparatus can include a touch-up component. The touch-up component can detect that at least one memory cell of a page of memory cells has lost a portion of a charge. The touch-up component can set touch-up parameters for the page of memory cells. The touch-up component can cause a transfer of data from the page of memory cells to a cache. The touch-up component can reprogram the at least one memory cell using the set touch-up parameters.

公开(公告)号：US20240062827A1

公开(公告)日：2024-02-22

申请号：US18234289

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Pitamber Shukla ,  Ching-Huang Lu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/102 ,  G11C16/26

Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.