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31.发明申请公开(公告)号：US20200006291A1
公开(公告)日：2020-01-02
申请号：US16020140
申请日：2018-06-27
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Scott E. Smith
IPC: H01L25/065 , H01L23/538 , G01R27/14
Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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公开(公告)号：US20190198127A1
公开(公告)日：2019-06-27
申请号：US15851129
申请日：2017-12-21
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Yu-Feng Chen , Scott E. Smith
CPC classification number: G11C17/16 , G11C7/1006 , G11C7/22 , G11C17/18 , G11C29/04 , G11C29/812
Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
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公开(公告)号：US10157661B1
公开(公告)日：2018-12-18
申请号：US15686996
申请日：2017-08-25
Applicant: Micron Technology, Inc.
Inventor： Michael V. Ho , Scott E. Smith
IPC: G11C11/24 , G11C11/4096 , G11C11/408 , G11C11/22 , G11C11/4094 , G11C11/4097 , G11C11/4091
Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.
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公开(公告)号：US08963604B2
公开(公告)日：2015-02-24
申请号：US14246328
申请日：2014-04-07
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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35.发明公开公开(公告)号：US20240281327A1
公开(公告)日：2024-08-22
申请号：US18441830
申请日：2024-02-14
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi , Scott E. Smith
CPC classification number: G06F11/1068 , G06F11/1435 , G06F13/1673
Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, both the metadata and the data may be provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.
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Patent Agency Ranking
公开(公告)号：US20240170088A1
公开(公告)日：2024-05-23
申请号：US18504302
申请日：2023-11-08
Applicant: Micron Technology, Inc.
Inventor： Scott E. Smith , Sujeet Ayyapureddi
IPC: G11C29/42
CPC classification number: G11C29/42
Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.
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37.发明公开公开(公告)号：US20240161856A1
公开(公告)日：2024-05-16
申请号：US18504324
申请日：2023-11-08
Applicant: Micron Technology, Inc.
Inventor： Scott E. Smith , Sujeet Ayyapureddi
CPC classification number: G11C29/42 , G11C29/1201 , G11C2029/1204
Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
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38.发明公开公开(公告)号：US20240160351A1
公开(公告)日：2024-05-16
申请号：US18504362
申请日：2023-11-08
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi , Scott E. Smith
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0634 , G06F3/0673
Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.
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公开(公告)号：US20240069589A1
公开(公告)日：2024-02-29
申请号：US17897957
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Kallol Mazumder , Navya Sri Sreeram , Scott E. Smith
Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
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公开(公告)号：US11908509B2
公开(公告)日：2024-02-20
申请号：US17701950
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： John E. Riley , Scott E. Smith , Jennifer E. Taylor , Gary L. Howe
IPC: G11C11/4076 , G11C11/4096
CPC classification number: G11C11/4076 , G11C11/4096
Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.
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