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    Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment
    32.
    发明申请
    Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment 有权
    使用高温化学处理形成其中具有均匀氮分布的含氮介电层

    公开(公告)号：US20070042559A1

    公开(公告)日：2007-02-22

    申请号：US11209140

    申请日：2005-08-22

    申请人： Hiroaki Niimi ,  Reima Laaksonen ,  Mahalingam Nandakumar

    发明人： Hiroaki Niimi ,  Reima Laaksonen ,  Mahalingam Nandakumar

    IPC分类号： H01L21/331

    CPC分类号： H01L27/11 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/8249

    摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.

    摘要翻译： 本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。 用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在 使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

    Method for forming halo/pocket implants through an L-shaped sidewall spacer
    33.
    发明申请
    Method for forming halo/pocket implants through an L-shaped sidewall spacer 审中-公开
    用于通过L形侧壁间隔件形成晕/窝植入物的方法

    公开(公告)号：US20060121681A1

    公开(公告)日：2006-06-08

    申请号：US11002764

    申请日：2004-12-02

    申请人： Mahalingam Nandakumar

    发明人： Mahalingam Nandakumar

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7833

    摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming an L-shaped spacer (410) proximate a sidewall of a gate structure (130) located over a substrate (110), and implanting halo/pocket implant regions (620) through the L-shaped spacer (410) and in the substrate (110).

    摘要翻译： 本发明提供一种半导体器件的制造方法及其制造方法。 除了其他步骤之外，用于制造半导体器件的方法包括在位于衬底（110）上方的栅极结构（130）的侧壁附近形成L形间隔物（410），并且注入卤素/口袋植入区域（620） 通过L形间隔物（410）和衬底（110）中。

    Combination test structures for in-situ measurements during fabrication of semiconductor devices
    37.
    发明授权
    Combination test structures for in-situ measurements during fabrication of semiconductor devices 有权
    用于半导体器件制造期间的原位测量的组合测试结构

    公开(公告)号：US6150669A

    公开(公告)日：2000-11-21

    申请号：US458208

    申请日：1999-12-09

    申请人： Mahalingam Nandakumar ,  Greg C. Baldwin ,  Andrew T. Appel

    发明人： Mahalingam Nandakumar ,  Greg C. Baldwin ,  Andrew T. Appel

    IPC分类号： H01L23/544 ,  H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L22/34

    摘要： A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.

    摘要翻译： 第一测试结构（40）用于测量栅极电阻/线宽和晶体管性能。 栅极线（42）与形成在栅极线（42）的任一侧上的源极（48）和漏极（50）区域的沟道区域（44）交叉。 栅极线（42）以H配置连接到四个探针焊盘（52），用于精确的线宽测量。 第二测试结构（70）可以单独使用或与第一测试结构结合使用。 单个栅极线（72）多次穿过一个护城河区域（74）。 这允许具有相同测试结构的电容和栅极栅极电阻测量以及更精确的TLD测量。

    Implant damage of layer for easy removal and reduced silicon recess
    38.
    发明授权
    Implant damage of layer for easy removal and reduced silicon recess 有权
    植入物损伤层易于去除和减少硅凹陷

    公开(公告)号：US07772094B2

    公开(公告)日：2010-08-10

    申请号：US12345414

    申请日：2008-12-29

    申请人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

    发明人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

    IPC分类号： H01L21/322

    CPC分类号： H01L21/76254 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139

    摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

    摘要翻译： 提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。 提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。 一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。 除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。 第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

    METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE
    39.
    发明申请
    METHOD OF FORMING SIDEWALL SPACERS TO REDUCE FORMATION OF RECESSES IN THE SUBSTRATE AND INCREASE DOPANT RETENTION IN A SEMICONDUCTOR DEVICE 有权
    形成侧壁间隔的方法，以减少在基底中形成的凹陷并增加半导体器件中的氘保持

    公开(公告)号：US20090286375A1

    公开(公告)日：2009-11-19

    申请号：US12122885

    申请日：2008-05-19

    申请人： Mahalingam Nandakumar ,  Said Ghneim ,  Frank Scott Johnson

    发明人： Mahalingam Nandakumar ,  Said Ghneim ,  Frank Scott Johnson

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28247 ,  H01L29/6656

    摘要： A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing an oxide layer covering the substrate and gate. Additionally, the substrate may be re-oxidized/annealing after forming the gate without depositing the oxide layer.

    摘要翻译： 在半导体器件中形成用于栅极的侧壁间隔物的方法包括：在栅极形成之后，再次氧化/退火衬底的硅和栅极的硅。 通过在惰性气氛或环境中进行退火，使基板再次氧化。 在沉积覆盖衬底和栅极的氧化物层之后，衬底可以被再氧化/退火。 此外，可以在形成栅极之后再次氧化/退火衬底，而不沉积氧化物层。

    Dual-counterdoped channel field effect transistor and method
    40.
    发明授权
    Dual-counterdoped channel field effect transistor and method 有权
    双对流通道场效应晶体管及方法

    公开(公告)号：US06960499B2

    公开(公告)日：2005-11-01

    申请号：US10866469

    申请日：2004-06-14

    申请人： Mahalingam Nandakumar ,  Karthik Vasanth ,  Ih-Chin Chen

    发明人： Mahalingam Nandakumar ,  Karthik Vasanth ,  Ih-Chin Chen

    IPC分类号： H01L21/265 ,  H01L29/10 ,  H01L21/336

    CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L29/1033

    摘要： A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

    摘要翻译： 公开了一种具有双重反向通道的场效应晶体管。 晶体管具有包括第一掺杂区域（28）和位于第一掺杂区域下方的第二掺杂区域（26）的沟道。 源极和漏极（32）形成在与沟道相邻的位置。 在本发明的一个实施例中，第一掺杂区域（28）掺杂有砷，而第二掺杂区域（26）掺杂有磷。 地下通道层（28）的高电荷载流子迁移率允许使用较低的沟道掺杂剂浓度，这又允许较低的源极/漏极口袋掺杂。 这降低了晶体管的电容和响应时间。