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    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
    31.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权
    具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏

    公开(公告)号：US20060246651A1

    公开(公告)日：2006-11-02

    申请号：US11118843

    申请日：2005-04-29

    申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

    Control of high-k gate dielectric film composition profile for property optimization
    32.
    发明授权
    Control of high-k gate dielectric film composition profile for property optimization 有权
    控制高k栅极电介质膜组成轮廓的性能优化

    公开(公告)号：US07071519B2

    公开(公告)日：2006-07-04

    申请号：US10338310

    申请日：2003-01-08

    申请人： Luigi Colombo ,  Mark Visokay ,  James Joseph Chambers ,  Antonio Luis Pacheco Rotondaro

    发明人： Luigi Colombo ,  Mark Visokay ,  James Joseph Chambers ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L29/94

    CPC分类号： H01L21/02271 ,  H01L21/28194 ,  H01L21/3142 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

    摘要： Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.

    摘要翻译： 公开了通过将介电层形成多个子层来促进形成具有特定组成分布的电介质层的方法和系统。 子层足够薄，使得可以为每个层实现特定的相对组成，因此，子层共同产生具有特定轮廓的介电层。 单个子层的形成通过控制影响相对组成的化学气相沉积工艺的一个或多个处理参数来实现。 可采用的一些加工参数包括晶片温度，压力和前体流速。

    Work function separation for fully silicided gates
    35.
    发明申请
    Work function separation for fully silicided gates 审中-公开
    完全硅化栅的工作功能分离

    公开(公告)号：US20070037333A1

    公开(公告)日：2007-02-15

    申请号：US11203716

    申请日：2005-08-15

    申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823835 ,  H01L21/823842

    摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal is added to a first region of polysilicon overlying a dielectric that is on a substrate, and a second metal is added to a second region of the polysilicon. A third metal is formed over the first and second regions and a silicidation process if performed to form a first alloy in the first region and a second alloy in the second region. First and second segregated regions are also established adjacent to the dielectric in the first and second regions, respectively. The first and second metals serve to shift or adjust respective values of first and second work functions in the first and second regions.

    摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，将第一金属添加到覆盖在衬底上的电介质上的多晶硅的第一区域中，并且将第二金属添加到多晶硅的第二区域。 在第一和第二区域上形成第三金属，如果在第一区域中形成第一合金并且在第二区域中形成第二合金，则形成硅化工艺。 第一和第二分离区域也分别在第一和第二区域中的电介质附近建立。 第一和第二金属用于移动或调整第一和第二区域中的第一和第二功函数的相应值。

    MOS transistor gates with doped silicide and methods for making the same
    36.
    发明授权
    MOS transistor gates with doped silicide and methods for making the same 有权
    具有掺杂硅化物的MOS晶体管栅极及其制造方法

    公开(公告)号：US07148546B2

    公开(公告)日：2006-12-12

    申请号：US10674771

    申请日：2003-09-30

    申请人： Mark Visokay ,  Luigi Colombo

    发明人： Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823835

    摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.

    摘要翻译： 提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。 上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在 上下金属硅化物。 可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。

    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon
    37.
    发明申请
    Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon 有权
    半导体CMOS器件和方法与NMOS高k电介质之间形成核心PMOS氮氧化硅介质形成之前，采用直接氮化硅

    公开(公告)号：US20060246647A1

    公开(公告)日：2006-11-02

    申请号：US11118842

    申请日：2005-04-29

    申请人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    发明人： Mark Visokay ,  Luigi Colombo ,  James Chambers

    IPC分类号： H01L21/8238 ,  H01L21/8242

    CPC分类号： H01L27/105 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11 ,  H01L27/1116

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

    摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成氧化物层。 氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 通过低温热处理在核心和I / O区域的PMOS区域内生长氮化硅层（516）。 随后，进行氧化处理（518），其将氮化硅氧化成氮氧化硅。

    Semiconductor structure and method of fabrication
    38.
    发明申请
    Semiconductor structure and method of fabrication 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20060202300A1

    公开(公告)日：2006-09-14

    申请号：US11394351

    申请日：2006-03-30

    申请人： Mark Visokay ,  Luigi Colombo

    发明人： Mark Visokay ,  Luigi Colombo

    IPC分类号： H01L29/00 ,  H01L21/302

    CPC分类号： H01L21/823842

    摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

    摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

    Dual work function gate electrodes obtained through local thickness-limited silicidation
    39.
    发明申请
    Dual work function gate electrodes obtained through local thickness-limited silicidation 有权
    通过局部厚度限制硅化获得的双功能功能栅电极

    公开(公告)号：US20060019437A1

    公开(公告)日：2006-01-26

    申请号：US10897846

    申请日：2004-07-23

    申请人： Robert Murto ,  Luigi Colombo ,  Mark Visokay

    发明人： Robert Murto ,  Luigi Colombo ,  Mark Visokay

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/823842

    摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.

    摘要翻译： 本发明提供一种制造半导体器件的方法。 除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135） 位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函 随之而来。