公开(公告)号：US20120127795A1

公开(公告)日：2012-05-24

申请号：US12949076

申请日：2010-11-18

申请人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Guan-Wei Wu ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.

摘要翻译： 提供一种非易失性存储器及其制造方法以及操作存储单元的方法。 非易失性存储器包括衬底，第一和第二掺杂区域，带电捕获结构，第一和第二栅极以及栅极间绝缘层。 第一和第二掺杂区域设置在衬底中并沿着第一方向延伸。 第一和第二掺杂区交替布置。 带电捕获结构设置在基板上。 第一和第二栅极设置在带电捕获结构上。 每个第一栅极位于第一掺杂区域之上。 第二栅极沿着第二方向延伸并且位于第二掺杂区域之上。 栅间绝缘层设置在第一栅极和第二栅极之间。 相邻的第一和第二掺杂区域和第一栅极，其间的第二栅极和带电捕获结构限定了存储单元。

公开(公告)号：US20120126307A1

公开(公告)日：2012-05-24

申请号：US12949092

申请日：2010-11-18

申请人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： GUAN-WEI WU ,  I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/76232

摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers.The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 非易失性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。 栅极结构设置在基板上。 栅极结构包括电荷存储结构，栅极和间隔物。 电荷存储结构设置在基板上。 栅极设置在电荷存储结构上。 间隔件设置在栅极和电荷存储结构的侧壁上。 第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。 隔离结构分别设置在栅极结构的两侧的基板中。

公开(公告)号：US08093665B2

公开(公告)日：2012-01-10

申请号：US12467479

申请日：2009-05-18

申请人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Guan-Wei Wu ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66636 ,  H01L29/665 ,  H01L29/7834

摘要： A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.

摘要翻译： 描述了一种半导体器件，其包括衬底，栅极结构，掺杂区域和轻掺杂区域。 基板具有阶梯状的上表面，其包括第一表面，第二表面和第三表面。 第二表面低于第一表面。 第三表面连接第一表面和第二表面。 栅极结构设置在第一表面上。 掺杂区域在栅极结构的两侧和第二表面的下方在衬底中配置。 轻掺杂区域分别配置在栅极结构和掺杂区域之间的衬底中。 每个轻掺杂区域包括彼此连接的第一部分和第二部分。 第一部分设置在第二表面下方，第二部分设置在第三表面下。

公开(公告)号：US20110216454A1

公开(公告)日：2011-09-08

申请号：US12719577

申请日：2010-03-08

申请人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Chia-Ling Lu ,  Yu-Lien Liu ,  Yan-Yu Chen ,  Che-Shih Lin ,  Tao-Cheng Lu

IPC分类号： H02H9/04 ,  H03H11/26

CPC分类号： H02H9/04 ,  H03H11/26

摘要： An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

摘要翻译： 描述了一种用于提供静电放电（ESD）保护的RC延迟电路。 电路使用NMOS晶体管和PMOS晶体管，使用相对小的电路布局面积产生大的有效电阻。

公开(公告)号：US20110080784A1

公开(公告)日：2011-04-07

申请号：US12574093

申请日：2009-10-06

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C16/3468 ,  G11C16/0466 ,  G11C16/10

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，根据第一阈值电压分布曲线和阈值电压辅助曲线分别将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。

公开(公告)号：US20100314680A1

公开(公告)日：2010-12-16

申请号：US12862020

申请日：2010-08-24

申请人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： I-Chen Yang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/76885 ,  H01L27/11568 ,  H01L29/4234

摘要： A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.

摘要翻译： 存储器阵列包括电荷存储结构，并且提供了电荷存储结构上的多个导电材料。 用作字线的每个导电材料具有基本上弧形的侧壁和基本上直的侧壁。

公开(公告)号：US07830707B2

公开(公告)日：2010-11-09

申请号：US11905211

申请日：2007-09-28

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US07692968B2

公开(公告)日：2010-04-06

申请号：US11782149

申请日：2007-07-24

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/26

摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

摘要翻译： 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US07348625B2

公开(公告)日：2008-03-25

申请号：US11194545

申请日：2005-08-02

申请人： Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L29/788

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

摘要翻译： EEPROM单元在电荷保持绝缘层的相对侧上包括第一和第二辅助栅极。 在EEPROM存储器单元中的电流在反应层之间流动，反应层响应于施加到辅助栅极的偏置而产生。 绝缘层可以包括氮化硅，其设置在沟道区域上方的二氧化硅层之间，使得这些层可以构成电介质叠层，其可被制造成占据相对小的面积。

公开(公告)号：US07193274B2

公开(公告)日：2007-03-20

申请号：US10854792

申请日：2004-05-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

摘要翻译： 在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制 电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。 基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。